Stress analysis method, wiring structure design method, program, and semiconductor device production method
    6.
    发明申请
    Stress analysis method, wiring structure design method, program, and semiconductor device production method 有权
    应力分析方法,接线结构设计方法,程序和半导体器件的制造方法

    公开(公告)号:US20070204243A1

    公开(公告)日:2007-08-30

    申请号:US11703218

    申请日:2007-02-07

    摘要: A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

    摘要翻译: 提供一种应力分析方法,包括:通过使用分割单元将芯片的内部划分为多个分析区域,通过使用复合特性导出单元导出多个分析区域的物理属性值的复合特性 基于多个分析区域中的每一个的布线结构数据,分析包括在分析区域中的材料,并且基于多个分析区域中的每一个,分别对每个分析区域进行复合,并且通过使用应力分析单元来创建三维模型 使用每个分析区域作为元素的有限元法,将复合属性应用于每个元素,并进行应力分析。

    Semiconductor device
    7.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号:US07067922B2

    公开(公告)日:2006-06-27

    申请号:US10809418

    申请日:2004-03-26

    IPC分类号: H01L23/48

    摘要: Disclosed is a semiconductor device including: a semiconductor substrate; at least one layer of a first insulating film formed above the semiconductor substrate and having a relative dielectric constant of 3.8 or less, an entire layer of the first insulating film being separated at least near four corners of the semiconductor substrate by a lacking portion that extends along the four corners; and a second insulating film covering a side face of the entire layer of the first insulating film in the lacking portion on a center side of the semiconductor substrate and having a relative dielectric constant of over 3.8.

    摘要翻译: 公开了一种半导体器件,包括:半导体衬底; 至少一层第一绝缘膜,形成在所述半导体衬底之上并具有3.8或更小的相对介电常数,所述第一绝缘膜的整个层被所述半导体衬底的至少四个角分离,所述缺陷部分延伸 沿四角; 以及第二绝缘膜,其覆盖半导体衬底的中心侧的缺损部分中的第一绝缘膜的整个层的侧面,并且具有超过3.8的相对介电常数。