公开(公告)号：US08283755B2

公开(公告)日：2012-10-09

申请号：US13067180

申请日：2011-05-13

申请人： Nobuo Hayasaka ,  Katsuya Okumura ,  Keiichi Sasaki ,  Mie Matsuo

发明人： Nobuo Hayasaka ,  Katsuya Okumura ,  Keiichi Sasaki ,  Mie Matsuo

IPC分类号： H01L29/40

CPC分类号： H01L23/642 ,  H01L21/76898 ,  H01L23/367 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/00

摘要： A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

摘要翻译： 公开了一种多芯片半导体器件，其中堆叠芯片，每个芯片包括形成在顶部的半导体衬底和电路部件，以及形成在半导体衬底的顶部上的层间绝缘膜。 至少一个芯片具有穿过半导体衬底和层间绝缘膜的通孔中形成的金属的连接插头。 具有连接插头的芯片通过该连接插头与另一个芯片电连接。

公开(公告)号：US08174093B2

公开(公告)日：2012-05-08

申请号：US12926104

申请日：2010-10-26

申请人： Nobuo Hayasaka ,  Katsuya Okumura ,  Keiichi Sasaki ,  Mie Matsuo

发明人： Nobuo Hayasaka ,  Katsuya Okumura ,  Keiichi Sasaki ,  Mie Matsuo

IPC分类号： H01L29/40

CPC分类号： H01L23/642 ,  H01L21/76898 ,  H01L23/367 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/00

摘要： A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

公开(公告)号：US20110215443A1

公开(公告)日：2011-09-08

申请号：US13067180

申请日：2011-05-13

申请人： Nobuo Hayasaka ,  Katsuya Okumura ,  Keiichi Sasaki ,  Mie Matsuo

发明人： Nobuo Hayasaka ,  Katsuya Okumura ,  Keiichi Sasaki ,  Mie Matsuo

IPC分类号： H01L29/41

CPC分类号： H01L23/642 ,  H01L21/76898 ,  H01L23/367 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/00

摘要： A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

公开(公告)号：US20110101522A1

公开(公告)日：2011-05-05

申请号：US12926104

申请日：2010-10-26

申请人： Nobuo Hayasaka ,  Katsuya Okumura ,  Keiichi Sasaki ,  Mie Matsuo

发明人： Nobuo Hayasaka ,  Katsuya Okumura ,  Keiichi Sasaki ,  Mie Matsuo

IPC分类号： H01L23/485

CPC分类号： H01L23/642 ,  H01L21/76898 ,  H01L23/367 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/00

摘要： A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

摘要翻译： 公开了一种多芯片半导体器件，其中堆叠芯片，每个芯片包括形成在顶部的半导体衬底和电路部件，以及形成在半导体衬底的顶部上的层间绝缘膜。 至少一个芯片具有穿过半导体衬底和层间绝缘膜的通孔中形成的金属的连接插头。 具有连接插头的芯片通过该连接插头与另一个芯片电连接。

公开(公告)号：US20080296165A1

公开(公告)日：2008-12-04

申请号：US12127653

申请日：2008-05-27

申请人： Junji KUNISAWA ,  Mitsuko ODAGAKI ,  Natsuki MAKINO ,  Koji MISHIMA ,  Kenji NAKAMURA ,  Hiroaki INOUE ,  Norio KIMURA ,  Tetsuo MATSUDA ,  Hisashi KANEKO ,  Nobuo HAYASAKA ,  Katsuya OKUMURA ,  Manabu TSUJIMURA ,  Toshiyuki MORITA

发明人： Junji KUNISAWA ,  Mitsuko ODAGAKI ,  Natsuki MAKINO ,  Koji MISHIMA ,  Kenji NAKAMURA ,  Hiroaki INOUE ,  Norio KIMURA ,  Tetsuo MATSUDA ,  Hisashi KANEKO ,  Nobuo HAYASAKA ,  Katsuya OKUMURA ,  Manabu TSUJIMURA ,  Toshiyuki MORITA

IPC分类号： C25D5/02

CPC分类号： H01L21/6719 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  C25D17/14 ,  H01L21/2885 ,  H01L21/67046 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/6715 ,  H01L21/6723 ,  H01L21/76877 ,  H01L21/76879 ,  H01L2924/0002 ,  H05K3/423 ,  H01L2924/00

摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.

摘要翻译： 用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。 该装置具有基板保持部分36，其水平地保持并旋转基板，其表面被面向上。 密封材料90接触表面的周缘部分，以水密的方式密封该部分。 阴极电极88在与基板接触时通过电流。 阴极部38与基板保持部36一体地旋转。电极臂部30在阴极部38的上方，水平且垂直地移动，阳极98面朝下。 将电镀液注入被镀表面与接近待镀表面的阳极98之间的空间中。 因此，电镀处理和附带的处理可以通过单个单元进行。

公开(公告)号：US07335517B2

公开(公告)日：2008-02-26

申请号：US10902391

申请日：2004-07-30

申请人： Nobuo Hayasaka ,  Katsuya Okumura ,  Keiichi Sasaki ,  Mie Matsuo

发明人： Nobuo Hayasaka ,  Katsuya Okumura ,  Keiichi Sasaki ,  Mie Matsuo

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/4763 ,  G01R31/26

CPC分类号： H01L23/642 ,  H01L21/76898 ,  H01L23/367 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/00

摘要： A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

摘要翻译： 公开了一种多芯片半导体器件，其中堆叠芯片，每个芯片包括形成在顶部的半导体衬底和电路部件，以及形成在半导体衬底顶部的层间绝缘膜。 至少一个芯片具有穿过半导体衬底和层间绝缘膜的通孔中形成的金属的连接插头。 具有连接插头的芯片通过该连接插头与另一个芯片电连接。

公开(公告)号：US06828684B2

公开(公告)日：2004-12-07

申请号：US10392967

申请日：2003-03-21

申请人： Hiroshi Ikegami ,  Rempei Nakata ,  Takashi Yoda ,  Nobuo Hayasaka ,  Yoshimi Hisatsune

发明人： Hiroshi Ikegami ,  Rempei Nakata ,  Takashi Yoda ,  Nobuo Hayasaka ,  Yoshimi Hisatsune

IPC分类号： H01L2348

CPC分类号： H01L23/53238 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02307 ,  H01L21/02315 ,  H01L21/3122 ,  H01L21/76838 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00011 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/19043 ,  H01L2924/30105 ,  Y10S438/959 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01004 ,  H01L2924/00014

摘要： There is provided a semiconductor device including a semiconductor substrate and a conductive layer above the semiconductor substrate, wherein the conductive layer contains copper, a surface region of the conductive layer contains at least one of C—H bonds and C—C bonds, and a total amount of C atoms forming the C—H bonds and C atoms forming the C—C bonds in the surface region is 30 atomic % or more of a whole amount of elements in the surface region.

摘要翻译： 提供一种半导体器件，其包括半导体衬底和在半导体衬底之上的导电层，其中导电层包含铜，导电层的表面区域包含CH键和CC键中的至少一个，并且总量C 形成CH键的原子和在表面区域中形成CC键的C原子在表面区域中的元素的总量为30原子％以上。

公开(公告)号：US6096631A

公开(公告)日：2000-08-01

申请号：US081010

申请日：1998-05-19

申请人： Kenro Nakamura ,  Rempei Nakata ,  Yusuke Kohyama ,  Nobuo Hayasaka

发明人： Kenro Nakamura ,  Rempei Nakata ,  Yusuke Kohyama ,  Nobuo Hayasaka

IPC分类号： H01L21/3205 ,  H01L21/304 ,  H01L21/321 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/3212 ,  H01L21/7684

摘要： The present invention provides a method of manufacturing a semiconductor device, including the steps of forming a first film on an entire surface of a substrate having a recessed portion, including a bottom surface and a side wall of the recessed portion, without completely filling the recessed portion, forming a second film on an entire surface of the first film such that the recessed portion, on the bottom surface and the side wall of which the first film is formed, is completely filled, and polishing the first and second films by a chemical-mechanical polishing method such that the substrate is exposed and the first and second films in the recessed portion remain.

摘要翻译： 本发明提供一种制造半导体器件的方法，包括以下步骤：在具有凹部的基板的整个表面上形成第一膜，该凹部包括凹部的底面和侧壁，而不完全填充凹部 在所述第一膜的整个表面上形成第二膜，使得形成所述第一膜的所述底面和所述第一膜的所述侧壁上的凹部被完全填充，并且通过化学品对所述第一膜和所述第二膜进行抛光 - 机械抛光方法，使得基板被暴露，并且凹部中的第一和第二膜保留。

公开(公告)号：US5424246A

公开(公告)日：1995-06-13

申请号：US99695

申请日：1993-07-30

申请人： Mie Matsuo ,  Haruo Okano ,  Nobuo Hayasaka ,  Kyoichi Suguro ,  Hideshi Miyajima ,  Jun-ichi Wada

发明人： Mie Matsuo ,  Haruo Okano ,  Nobuo Hayasaka ,  Kyoichi Suguro ,  Hideshi Miyajima ,  Jun-ichi Wada

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L23/532 ,  H01L21/205

CPC分类号： H01L21/76877 ,  H01L21/28518 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/12044

摘要： According to this invention, there is provided a method of forming a groove wiring layer, including the steps of forming a metal oxide film, consisting of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of a hydrogen oxide or of a carbon oxide, on an insulating film formed on a semiconductor substrate, and reducing the metal oxide film to form an electrode-wiring layer consisting of a metal which is a main component constituting the metal oxide. In this manner, an electrode-wiring layer having high EM and SM resistances without causing an increase in electric resistivity caused by an impurity or the like can be obtained.

摘要翻译： 根据本发明，提供一种形成沟槽布线层的方法，包括形成金属氧化物膜的步骤，该金属氧化物膜由标准自由能降低的金属氧化物组成，其小于氢的标准自由能的降低 氧化物或碳氧化物，在形成于半导体衬底上的绝缘膜上，还原金属氧化物膜，形成由作为构成金属氧化物的主要成分的金属构成的电极配线层。 以这种方式，可以获得具有高EM和SM电阻而不引起由杂质引起的电阻率增加的电极布线层等。

公开(公告)号：US20080251385A1

公开(公告)日：2008-10-16

申请号：US12116562

申请日：2008-05-07

申请人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

发明人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

IPC分类号： C25D21/12

CPC分类号： H01L21/6719 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  C25D17/14 ,  H01L21/2885 ,  H01L21/67046 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/6715 ,  H01L21/6723 ,  H01L21/76877 ,  H01L21/76879 ,  H01L2924/0002 ,  H05K3/423 ,  H01L2924/00

摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.

摘要翻译： 用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。 该装置具有基板保持部分36，其水平地保持并旋转基板，其表面被面向上。 密封材料90接触表面的周缘部分，以水密的方式密封该部分。 阴极电极88在与基板接触时通过电流。 阴极部38与基板保持部36一体旋转。 电极臂部分30在阴极部分38的上方并且可水平和垂直地移动，并且阳极98面向下。 将电镀液注入被镀表面与接近待镀表面的阳极98之间的空间中。 因此，电镀处理和附带的处理可以通过单个单元进行。