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1.发明授权Video display apparatus for displaying a plurality of video signals having different scanning frequencies and a multi-screen display system using the video display apparatus 失效用于显示具有不同扫描频率的多个视频信号的视频显示装置和使用该视频显示装置的多屏显示系统
公开(公告)号：US5557342A
公开(公告)日：1996-09-17
申请号：US425698
申请日：1995-04-19
申请人： Masahiro Eto , Hiroyuki Urata , Fumio Inoue , Masanori Ogino , Atsushi Maruyama , Kiyoshi Yamamoto
发明人： Masahiro Eto , Hiroyuki Urata , Fumio Inoue , Masanori Ogino , Atsushi Maruyama , Kiyoshi Yamamoto
摘要： A video display system that includes a housing has arranged thereon a plurality of video input terminals for receiving a plurality of video signals having different scanning frequencies. An expansion/compression processing circuit replaceably mounted on the housing receives and expands/compresses the plurality of video signals and produces at least one video signal expanded/compressed in synchronism with a sync signal selected by a sync switching circuit. At least one of the video signals is synthesized with another video signal, and the synthesized video signal is produced by a video signal synthesis circuit. A video signal from the video signal synthesis circuit is used to generate a video display signal in synchronism with the sync signal. This video display signal is applied to a display. At least one such video display system, an AV controller, a central control console and a lecture table are combined to realize a screen display system.
摘要翻译： 包括壳体的视频显示系统在其上布置有用于接收具有不同扫描频率的多个视频信号的多个视频输入端子。 可替换地安装在壳体上的扩展/压缩处理电路接收并扩展/压缩多个视频信号，并且产生与由同步切换电路选择的同步信号同步地扩展/压缩的至少一个视频信号。 视频信号中的至少一个与另一个视频信号合成，合成的视频信号由视频信号合成电路产生。 来自视频信号合成电路的视频信号用于与同步信号同步产生视频显示信号。 该视频显示信号被应用于显示器。 组合至少一个这样的视频显示系统，AV控制器，中央控制台和讲座，以实现屏幕显示系统。
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公开(公告)号：US5541665A
公开(公告)日：1996-07-30
申请号：US362241
申请日：1994-12-22
申请人： Hiroyuki Urata , Masahiro Eto , Atsushi Maruyama , Fumio Inoue , Masanori Ogino , Kiyoshi Yamamoto , Kazutaka Naka , Masaaki Iwanaga
发明人： Hiroyuki Urata , Masahiro Eto , Atsushi Maruyama , Fumio Inoue , Masanori Ogino , Kiyoshi Yamamoto , Kazutaka Naka , Masaaki Iwanaga
CPC分类号： H04N7/125 , H04N11/006 , H04N7/0105 , H04N5/126 , H04N5/46
摘要： In order to enable sampling of high definition still video signals in addition to common video signals, a function is added for sampling video signals with every other plurality of picture elements as an interval to an image processing apparatus without using a sampling circuit which requires high speed operations. The invention is also intended to change over between two circuits that is, a circuit for using a picture element clock regenerated by a PLL circuit as a sampling clock for analog to digital converters and a circuit for using a clock obtained by dividing the picture element clock as a sampling clock for the analog to digital converters to sample video signals with every other plurality of picture elements as an interval. Thus, it is possible to carry out sampling of high definition video signals with high frequencies in addition to common video signals without necessity of raising the operating speed of the sampling circuit.
摘要翻译： 为了能够对公共视频信号进行高分辨率静止图像信号的采样，添加了将图像信号与其他多个像素一起作为图像处理装置的间隔进行采样的功能，而不使用需要高速的采样电路 操作。 本发明还旨在在两个电路之间切换，即，用于使用由PLL电路再生的像素时钟作为模数转换器的采样时钟的电路和用于使用通过将图像元素时钟 作为模数转换器的采样时钟，以与其他多个像素作为间隔采样视频信号。 因此，除了公共视频信号之外，可以对高频高清晰度视频信号进行采样，而不需要提高采样电路的工作速度。
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公开(公告)号：US6107984A
公开(公告)日：2000-08-22
申请号：US805730
申请日：1997-02-25
IPC分类号： H04N5/46 , G06F3/14 , G09G1/16 , G09G5/00 , G09G5/12 , G09G5/18 , H04N5/073 , H04N5/12 , H04N5/74 , H04N9/12 , G09G3/36
CPC分类号： G09G5/12 , G09G1/16 , H04N5/073 , H04N9/12 , G06F3/1446 , G09G2340/0407 , H04N5/126 , H04N9/3147
摘要： A video signal processor for outputting a video signal based on an output horizontal synchronizing signal and an output vertical synchronizing signal. The processor includes a circuit inputting a reference horizontal synchronizing signal, a circuit inputting a reference vertical synchronizing signal, a circuit generating an output horizontal synchronizing signal having a frequency different from that of the reference horizontal synchronizing signal, and a circuit generating an output vertical synchronizing signal synchronized in phase with the reference vertical synchronizing signal.
摘要翻译： 一种用于基于输出水平同步信号和输出垂直同步信号输出视频信号的视频信号处理器。 处理器包括输入参考水平同步信号的电路，输入参考垂直同步信号的电路，产生具有与参考水平同步信号的频率不同的频率的输出水平同步信号的电路，以及产生输出垂直同步信号的电路 信号与参考垂直同步信号同相同步。
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4.发明授权Video signal processing device for automatically adjusting phase of sampling clocks 失效用于自动调整采样时钟相位的视频信号处理装置公开(公告)号：US06917388B2
公开(公告)日：2005-07-12
申请号：US10071148
申请日：2002-02-11
IPC分类号： G09G5/18 , H03L7/081 , H03L7/199 , H04N5/04 , H04N5/12 , H04N5/20 , H03L1/12 , H03M1/12 , H04N7/00 , H04N9/475
摘要： In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.
摘要翻译： 在视频信号处理装置中，代表具有黑白两种灰度的测试图形的输入视频信号VO与A / D转换器4同步地与写入控制电路中产生的采样时钟同步地转换为8位数据 5，然后存储在存储器6中。 MPU9读出存储在存储器6中的视频信号的有效区域中的像素数据，并且计算其值大于预定值的白电平图像元数据的平均值与平均值之间的差ΔT 其值小于预定值的黑电平图像元素数据以及白电平图像元素数据的方差与黑电平图像元素数据的方差之间的总方差VT。 MPU9控制在写入控制电路5中产生的采样时钟的相位，使得AT最大，VT最小。 通过此操作，当视频信号转换为数字数据时，采样相位可以自动调整为最佳值。
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5.发明授权Video signal processing device for automatically adjusting phase of sampling clocks 失效用于自动调整采样时钟相位的视频信号处理装置公开(公告)号：US06707503B1
公开(公告)日：2004-03-16
申请号：US09225348
申请日：1999-01-05
IPC分类号： H03L700
摘要： In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.
摘要翻译： 在视频信号处理装置中，代表具有黑白两种灰度的测试图形的输入视频信号VO与A / D转换器4同步地与写入控制电路中产生的采样时钟同步地转换为8位数据 MPU 9存储在存储器6中的视频信号的有效区域中读出图像元素数据，并计算出在其值为0的白电平像素数据的平均值之间的差ΔT 大于预定值，并且其值小于预定值的黑电平图像元素数据的平均值，以及白电平图像元素数据的方差与黑电平的方差之间的总方差VT 图片元素数据。 MPU9控制在写入控制电路5中产生的采样时钟的相位，使得AT最大，VT最小。 通过此操作，当视频信号转换为数字数据时，采样相位可以自动调整为最佳值。
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6.发明授权Video signal processing device for automatically adjusting phase of sampling clocks 失效用于自动调整采样时钟相位的视频信号处理装置
公开(公告)号：US5990968A
公开(公告)日：1999-11-23
申请号：US687240
申请日：1996-07-25
IPC分类号： G06F1/10 , G09G5/18 , H03L7/081 , H03L7/091 , H03L7/199 , H04N5/04 , H04N5/12 , H04N5/20 , H04N5/66 , H04N9/64 , H03L7/00 , H04L7/00
摘要： In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.
摘要翻译： 在视频信号处理装置中，代表具有黑白两种灰度的测试图形的输入视频信号VO与A / D转换器4同步地与写入控制电路中产生的采样时钟同步地转换为8位数据 MPU 9存储在存储器6中的视频信号的有效区域中读出图像元素数据，并计算出在其值为0的白电平像素数据的平均值之间的差ΔT 大于预定值，并且其值小于预定值的黑电平图像元素数据的平均值，以及白电平图像元素数据的方差与黑电平的方差之间的总方差VT 图片元素数据。 MPU9控制在写入控制电路5中产生的采样时钟的相位，使得AT最大，VT最小。 通过此操作，当视频信号转换为数字数据时，采样相位可以自动调整为最佳值。
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7.发明授权Processor for converting pixel number of video signal and display apparatus using the same 失效用于转换视频信号的像素数和使用其的显示装置的处理器
公开(公告)号：US5986635A
公开(公告)日：1999-11-16
申请号：US837747
申请日：1997-04-22
申请人： Kazutaka Naka , Atsushi Maruyama , Hiroyuki Urata , Haruki Takata
发明人： Kazutaka Naka , Atsushi Maruyama , Hiroyuki Urata , Haruki Takata
CPC分类号： G09G5/008 , G09G5/005 , G09G2300/026 , G09G2340/0414 , G09G2340/0421 , G09G2340/0442 , G09G5/006
摘要： A video signal processor which includes a circuit for converting the number of lines in a digitized video signal, a circuit for generating a display dot clock, a circuit for outputting analog pixel data subjected to a line number conversion and having a frequency different from that of the display dot clock, and a circuit for smoothing the analog pixel data; and in which a frequency fck of the display dot clock, an output frequency frk of the analog pixel data and a frequency fho of the horizontal synchronization signal satisfies an equation;frck/N=fck/M=fhowhere M and N are natural numbers satisfying M.noteq.N.
摘要翻译： 一种视频信号处理器，包括用于转换数字化视频信号中的行数的电路，用于产生显示点时钟的电路，用于输出经过行数转换的模拟像素数据的电路，并且具有不同于 显示点时钟和用于平滑模拟像素数据的电路; 并且其中显示点时钟的频率fck，模拟像素数据的输出频率frk和水平同步信号的频率fho满足等式; frck / N = fck / M = fho其中M和N是满足的自然数 M NOTEQUAL N.
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公开(公告)号：US20080143637A1
公开(公告)日：2008-06-19
申请号：US11802631
申请日：2007-05-24
申请人： Yusuke Sunahara , Hiroyuki Urata , Satoshi Shibuya
发明人： Yusuke Sunahara , Hiroyuki Urata , Satoshi Shibuya
IPC分类号： G09G5/00
CPC分类号： G06F3/1446 , G09G3/2096 , G09G5/008
摘要： A phase shifter is provided to adjust the phase of the pixel clock generated by a PLL to the data of the digital image signal regenerated by a digital interface receiver circuit. The pixel clock which is output from the phase shifter is used as a pixel clock in a digital interface transmitter circuit.
摘要翻译： 提供了一种移相器，用于将由PLL生成的像素时钟的相位调整为由数字接口接收器电路再生的数字图像信号的数据。 从移相器输出的像素时钟用作数字接口发射机电路中的像素时钟。
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