摘要:
In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.
摘要:
In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.
摘要:
In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.
摘要:
In order to enable sampling of high definition still video signals in addition to common video signals, a function is added for sampling video signals with every other plurality of picture elements as an interval to an image processing apparatus without using a sampling circuit which requires high speed operations. The invention is also intended to change over between two circuits that is, a circuit for using a picture element clock regenerated by a PLL circuit as a sampling clock for analog to digital converters and a circuit for using a clock obtained by dividing the picture element clock as a sampling clock for the analog to digital converters to sample video signals with every other plurality of picture elements as an interval. Thus, it is possible to carry out sampling of high definition video signals with high frequencies in addition to common video signals without necessity of raising the operating speed of the sampling circuit.
摘要:
A video signal processor for outputting a video signal based on an output horizontal synchronizing signal and an output vertical synchronizing signal. The processor includes a circuit inputting a reference horizontal synchronizing signal, a circuit inputting a reference vertical synchronizing signal, a circuit generating an output horizontal synchronizing signal having a frequency different from that of the reference horizontal synchronizing signal, and a circuit generating an output vertical synchronizing signal synchronized in phase with the reference vertical synchronizing signal.
摘要:
A video signal processor which includes a circuit for converting the number of lines in a digitized video signal, a circuit for generating a display dot clock, a circuit for outputting analog pixel data subjected to a line number conversion and having a frequency different from that of the display dot clock, and a circuit for smoothing the analog pixel data; and in which a frequency fck of the display dot clock, an output frequency frk of the analog pixel data and a frequency fho of the horizontal synchronization signal satisfies an equation;frck/N=fck/M=fhowhere M and N are natural numbers satisfying M.noteq.N.
摘要翻译:一种视频信号处理器,包括用于转换数字化视频信号中的行数的电路,用于产生显示点时钟的电路,用于输出经过行数转换的模拟像素数据的电路,并且具有不同于 显示点时钟和用于平滑模拟像素数据的电路; 并且其中显示点时钟的频率fck,模拟像素数据的输出频率frk和水平同步信号的频率fho满足等式; frck / N = fck / M = fho其中M和N是满足的自然数 M NOTEQUAL N.
摘要:
A CRT display device capable of displaying a signal from the existing image signal source, in which a vertical frequency is approximately fixed and a horizontal frequency is widely distributed beyond a ratio of 3:1, on one image screen. The CRT display device includes a scan converter unit and a display unit. The scan converter unit includes an output horizontal frequency unifying circuit, a horizontal blanking period ratio converting circuit, a vertical frequency converting unit and a vertical blanking period ratio converting circuit. The display unit includes a vertical deflection circuit and a circuit for correcting a vertical S-shaped distortion. In a phase synchronous circuit, a lock-out detector is connected to an output of a three state output digital phase detector, and on the basis of an output thereof, a switch is subjected to the "ON"/"OFF" control. For a period of time when an output of the lock-out detector indicates a lock-out state, a loop gain of the PLL is increased and the pull-in time is shortened. For the remaining periods of time, i.e., in the steady state, the loop gain is decreased and the noise resistance characteristics are improved.
摘要:
The system is made up of signal conversion unit for converting a video signal into two-line sum signal and difference signal for every two lines, time base conversion unit for time base converting the signals so that the transmission band of the difference signal is lower than the transmission band of the sum signal, and signal multiplexing unit for time-sharing multiplexing a time base converted sum signal and a time base converted difference signal.
摘要:
A color image display apparatus which supplies red, green, and blue color video signals to respective red, green, and blue light emitting cells and performs color image display. Assuming that time response characteristics of light emission by red, green, and blue light emitting cells have respective values TR, TG, and TB, and |X| represents an absolute value of X, then |TR-TG|
摘要:
A color image display apparatus which supplies red, green and blue color video signals to respective red, green and blue light emitting cells and performs color image display. Assuming that time response characteristics of light emission by red, green and blue light emitting cells have respective values TR, TG and TB, and |X| represents absolute value of X, then, |TR−TG|