公开(公告)号：US5423072A

公开(公告)日：1995-06-06

申请号：US89374

申请日：1993-07-12

申请人： Masakazu Iwashita ,  Osamu Kojima

发明人： Masakazu Iwashita ,  Osamu Kojima

IPC分类号： H04B7/26 ,  G01R29/10 ,  H01Q1/42 ,  H01Q19/10 ,  H04B17/00 ,  H04W24/00

CPC分类号： H01Q19/108 ,  G01R29/10 ,  H01Q1/42 ,  H04B17/103 ,  H04B17/16

摘要： In sector cell base stations, directive antennae with box-shaped reflectors are widely used. By way of a testing antenna incorporated such a reflector box, stable and appropriate electromagnetic coupling to the antenna elements of the directive antenna can be realized and undesirable coupling from outside the reflector box can be prevented, thereby improving the reliability of the testing system.

摘要翻译： 在扇区小区基站中，广泛使用具有盒形反射器的指令天线。 通过结合这样的反射器盒的测试天线，可以实现对定向天线的天线元件的稳定和适当的电磁耦合，并且可以防止从反射器盒外部的不期望的耦合，从而提高测试系统的可靠性。

公开(公告)号：US5194764A

公开(公告)日：1993-03-16

申请号：US627058

申请日：1990-12-13

申请人： Junji Yano ,  Tsukasa Miyawaki ,  Masami Atoh ,  Masakazu Gotou ,  Masakazu Iwashita ,  Michio Kaji

发明人： Junji Yano ,  Tsukasa Miyawaki ,  Masami Atoh ,  Masakazu Gotou ,  Masakazu Iwashita ,  Michio Kaji

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/0948

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/108

摘要： A data output buffer circuit for a semiconductor integrated circuit has a plurality of output buffer circuits. Each output buffer circuit has an input terminal for receiving input data and an output buffer having first and second switching circuits serially connected between two high and low power source terminals. Each of the first and second switching circuits has a control terminal for turning on and off each of the first and second switching circuits upon receipt of a control signal at the control terminals. A timing signal input terminal receives a timing signal with which the output buffer circuit operates in synchronism. A timing switch connects the next stage of the input terminal and is turned on by the timing signal. A delay signal is connected between the timing switch means and the control terminals of the first and second switching circuits and delays the input data from the input terminal and transmits the delayed input data to the control terminals of the first and second switching circuits. The delay time of the delay circuit of one of the output buffer circuits is different from the delay time of another of the output buffer circuits. An output terminal connects to the interconnection between the first and second switching circuits.