公开(公告)号：US4231108A

公开(公告)日：1980-10-28

申请号：US48256

申请日：1979-06-13

申请人： Masao Suzuki ,  Toshio Hayashi ,  Kuniyasu Kawarada ,  Kazuhiro Toyoda ,  Chikai Ono

发明人： Masao Suzuki ,  Toshio Hayashi ,  Kuniyasu Kawarada ,  Kazuhiro Toyoda ,  Chikai Ono

IPC分类号： G11C5/06 ,  G11C11/411 ,  G11C11/415 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8226 ,  H01L23/52 ,  H01L27/04 ,  H01L27/082 ,  H01L27/102 ,  G11C11/40

CPC分类号： H01L27/1025 ,  G11C11/4113 ,  G11C11/415 ,  G11C5/063

摘要： An improved semiconductor integrated circuit device having a memory cell array formed of integrated injection logic memory cells. The semiconductor integrated circuit according to the present invention includes integration injection logic memory cells which are arranged in matrix form, word lines and bit lines which are connected to the memory cells arranged in the row or column directions, one of the word lines being formed by a semiconductor bulk, current sources provided at least at both ends of the word lines or the bit lines.

摘要翻译： 一种改进的半导体集成电路器件，具有由集成注入逻辑存储单元形成的存储单元阵列。 根据本发明的半导体集成电路包括以矩阵形式布置的集成注入逻辑存储单元，连接到以行或列方向布置的存储单元的字线和位线，其中一条字线由 半导体本体，至少在字线或位线的两端提供电流源。

公开(公告)号：US4228525A

公开(公告)日：1980-10-14

申请号：US38016

申请日：1979-05-11

申请人： Kuniyasu Kawarada ,  Masao Suzuki ,  Chikai Ono ,  Kazuhiro Toyoda

发明人： Kuniyasu Kawarada ,  Masao Suzuki ,  Chikai Ono ,  Kazuhiro Toyoda

IPC分类号： G11C5/06 ,  G11C11/411 ,  H01L27/102 ,  G11C11/40

CPC分类号： H01L27/1025 ,  G11C11/4113 ,  G11C5/063

摘要： A semiconductor integrated circuit device has an array of memory cells formed by integrated injection logic. A desired number of dummy cells are provided at both ends of each line of the array, so that a write current, which flows when the memory cell near the dummy cell is selected, is shunted by the dummy cell, thereby the currents which flow in the memory cells in the line of the memory array are equalized.

摘要翻译： 半导体集成电路器件具有由集成注入逻辑形成的存储单元阵列。 在阵列的每一行的两端设置所需数量的虚设单元，从而在虚拟单元附近的存储单元被选择时流入的写入电流被虚设的单元分流，从而流入 存储器阵列的行中的存储器单元被均衡。