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1.发明授权
公开(公告)号：US5276634A
公开(公告)日：1994-01-04
申请号：US748191
申请日：1991-08-20
申请人： Masato Suzuki , Mikako Yasutome , Hideyo Tsuruta
发明人： Masato Suzuki , Mikako Yasutome , Hideyo Tsuruta
CPC分类号： G06F7/485 , G06F7/483 , G06F7/4876 , G06F7/49936 , G06F7/49957
摘要： A data processing apparatus and method for floating point data used in a central processing unit for a digital computer effects the four fundamental arithmetic computations of floating point data and the rounding and normalizing computations. In the case of the floating point addition or subtraction, the mantissa portion of the two floating point data and a generated round addition value are summed using a single adder and, in the case of multiplication, a sum output and a carry output of a multiplying unit and a generated round addition value are added using a single adder, so as to correct the least significant bit of the output of the adder or the round addition value is again added. Since the need of effecting readdition for rounding is small, the average processing step numbers becomes small in comparison with the conventional techniques, and, since the mantissa operation and rounding are effected using the same adder at the same time, less hardware is required.
摘要翻译： 用于数字计算机的中央处理单元中使用的浮点数据的数据处理装置和方法执行浮点数据的四个基本算术运算和舍入和归一化计算。 在浮点加法或减法的情况下，使用单个加法器将两个浮点数据的尾数部分和生成的加法相加，并且在乘法的情况下，乘法运算的和输出和进位输出 使用单个加法器添加单位和生成的舍入加法值，以便校正加法器的输出的最低有效位或再次相加循环加法值。 由于需要进行舍入的再现，所以与常规技术相比，平均处理步骤数变小，并且由于使用相同的加法器同时进行尾数运算和舍入，所以需要较少的硬件。
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公开(公告)号：US07903885B2
公开(公告)日：2011-03-08
申请号：US11259132
申请日：2005-10-27
申请人： Hideyo Tsuruta
发明人： Hideyo Tsuruta
CPC分类号： H04N19/423 , H04N19/61
摘要： A data converting apparatus includes a video encode or decode operation unit which decodes a bit stream into a video signal; an IO buffer into which the bit stream transferred from an encoded-video recorder is stored; and a DMAC which controls a process of determining, in accordance with free space of the IO buffer and an OP buffer, either a first path going through a main memory or a second path bypassing the main memory as the transfer path, and having the bit stream, that is stored in the IO buffer, inputted into the video encode or decode operation unit via the determined transfer path.
摘要翻译： 数据转换装置包括将比特流解码为视频信号的视频编码或解码操作单元; 存储从编码视频记录器传送的比特流的IO缓冲器; 以及DMAC，其控制根据IO缓冲器和OP缓冲器的自由空间确定经过主存储器的第一路径或者绕过主存储器的第二路径作为传送路径的处理，并且具有位 存储在IO缓冲器中的流经由确定的传送路径输入到视频编码或解码操作单元。
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公开(公告)号：US07716391B2
公开(公告)日：2010-05-11
申请号：US11382379
申请日：2006-05-09
申请人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
发明人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
IPC分类号： G06F3/00
CPC分类号： G06F3/0221 , G06F13/28 , Y02D10/14
摘要： A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information obtainment unit which obtains the commands from the command queue; a grouping unit which groups the held commands, based on a source and a destination designated in each of the obtained commands; a schedule unit which decides an order of issuing the commands sequentially from a group having more command, as a priority; and a selector which selects a command to be issued according to the decided order.
摘要翻译： 根据本发明的数据传送装置具有： DMAC和另一个DMAC，其通过多个总线之间的直接存储器访问来传送数据; 作为队列保存用于指示数据传送的命令的命令队列; 总线信息获取单元，其从命令队列获取命令; 分组单元，其基于在每个所获得的命令中指定的源和目的地对保持的命令进行分组; 作为优先级，从具有更多命令的组中顺序地确定发出命令的顺序的调度单元; 以及选择器，其根据所决定的顺序选择要发出的命令。
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公开(公告)号：US20060101484A1
公开(公告)日：2006-05-11
申请号：US11253683
申请日：2005-10-20
IPC分类号： H04N7/16
摘要： The decoding apparatus in the present invention includes a memory operable to hold encoded data representing one of a compressed sound and a compressed image, a memory read-out unit operable to sequentially read out the encoded data from said memory, a match determining circuit operable to determine whether or not data matching a specific bit sequence exists in the encoded data read out by said memory read-out unit, a deleting circuit operable to delete a part of the specific bit sequence from the encoded data read out from said memory, when said match determining circuit determines that the specific bit sequence exists, and a decoding circuit operable to decode the post-deletion encoded data.
摘要翻译： 本发明的解码装置包括：存储器，用于保存表示压缩声音和压缩图像之一的编码数据;存储器读出单元，可操作以从所述存储器顺序读出编码数据;匹配确定电路， 确定在由所述存储器读出单元读出的编码数据中是否存在与特定比特序列匹配的数据，删除电路，用于当从所述存储器读出的编码数据中删除特定比特序列的一部分时， 匹配确定电路确定特定比特序列存在，并且解码电路可操作以解码后删除编码数据。
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公开(公告)号：US20060098730A1
公开(公告)日：2006-05-11
申请号：US11259132
申请日：2005-10-27
申请人： Hideyo Tsuruta
发明人： Hideyo Tsuruta
CPC分类号： H04N19/423 , H04N19/61
摘要： A video codec is composed of: a video encode/decode operation unit which decodes a bitstream into a video signal; an IO buffer into which the bitstream transferred from an encoded-video recorder is stored; and a DMAC which controls a process of determining, in accordance with free space of the IO buffer and an OP buffer, either a first path going through a main memory or a second path bypassing the main memory 11 as the transfer path, and having the bitstream, that is stored in the IO buffer, inputted into the video encode/decode operation unit via the determined transfer path.
摘要翻译： 视频编解码器包括：将比特流解码为视频信号的视频编码/解码操作单元; 存储从编码视频记录器传送的比特流到其中的IO缓冲器; 以及DMAC，其控制根据IO缓冲器和OP缓冲器的自由空间确定经过主存储器的第一路径或绕过主存储器11作为传送路径的第二路径的处理，并且具有 存储在IO缓冲器中的比特流通过确定的传送路径输入到视频编码/解码操作单元。
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6.发明授权Decoding apparatus and encoding apparatus with specific bit sequence deletion and insertion 失效具有特定位序列删除和插入的解码装置和编码装置公开(公告)号：US07668381B2
公开(公告)日：2010-02-23
申请号：US11253683
申请日：2005-10-20
IPC分类号： G06K9/36
摘要： The decoding apparatus in the present invention includes a memory operable to hold encoded data representing one of a compressed sound and a compressed image, a memory read-out unit operable to sequentially read out the encoded data from said memory, a match determining circuit operable to determine whether or not data matching a specific bit sequence exists in the encoded data read out by said memory read-out unit, a deleting circuit operable to delete a part of the specific bit sequence from the encoded data read out from said memory, when said match determining circuit determines that the specific bit sequence exists, and a decoding circuit operable to decode the post-deletion encoded data.
摘要翻译： 本发明的解码装置包括：存储器，用于保存表示压缩声音和压缩图像之一的编码数据;存储器读出单元，可操作以从所述存储器顺序读出编码数据;匹配确定电路， 确定在由所述存储器读出单元读出的编码数据中是否存在与特定比特序列匹配的数据，删除电路，用于当从所述存储器读出的编码数据中删除特定比特序列的一部分时， 匹配确定电路确定特定比特序列存在，并且解码电路可操作以解码后删除编码数据。
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公开(公告)号：US20060259662A1
公开(公告)日：2006-11-16
申请号：US11382379
申请日：2006-05-09
申请人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
发明人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
IPC分类号： G06F3/00
CPC分类号： G06F3/0221 , G06F13/28 , Y02D10/14
摘要： A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information obtainment unit which obtains the commands from the command queue; a grouping unit which groups the held commands, based on a source and a destination designated in each of the obtained commands; a schedule unit which decides an order of issuing the commands sequentially from a group having more command, as a priority; and a selector which selects a command to be issued according to the decided order.
摘要翻译： 根据本发明的数据传送装置具有： DMAC和另一个DMAC，其通过多个总线之间的直接存储器访问来传送数据; 作为队列保存用于指示数据传送的命令的命令队列; 总线信息获取单元，其从命令队列获取命令; 分组单元，其基于在每个所获得的命令中指定的源和目的地对保持的命令进行分组; 作为优先级，从具有更多命令的组中顺序地确定发出命令的顺序的调度单元; 以及选择器，其根据所决定的顺序选择要发出的命令。
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8.发明授权First-in-first-out (FIFO) memory device for inputting/outputting data with variable lengths 失效先进先出（FIFO）存储器，用于输入/输出具有可变长度的数据公开(公告)号：US06442646B1
公开(公告)日：2002-08-27
申请号：US09050107
申请日：1998-03-30
申请人： Hideyo Tsuruta
发明人： Hideyo Tsuruta
IPC分类号： G06F1200
CPC分类号： G06F5/08
摘要： A FIFO memory device for inputting/outputting data having variable lengths of the present invention, includes: a first holding portion for holding data having a maximum data length MAX of input data to be input to the FIFO memory device; a second holding portion for holding residue data having a data length shorter than the maximum data length; and an input selecting portion for selectively inputting the input data to the first holding portion and the second holding portion in accordance with a data length IBP of the residue data and a data length WB of the input data.
摘要翻译： 一种用于输入/输出具有本发明可变长度的数据的FIFO存储器件，包括：第一保持部分，用于保存要输入到FIFO存储器件的输入数据的最大数据长度MAX的数据; 第二保持部，用于保持数据长度短于最大数据长度的残差数据; 以及输入选择部分，用于根据剩余数据的数据长度IBP和输入数据的数据长度WB有选择地将输入数据输入到第一保持部分和第二保持部分。
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9.发明授权Iterative high radix divider decoding the upper bits of a divisor and dividend 失效重组高分辨率分解器（DIVIDER）解码分部和部分的上位
公开(公告)号：US5206827A
公开(公告)日：1993-04-27
申请号：US682902
申请日：1991-04-09
申请人： Hideyo Tsuruta
发明人： Hideyo Tsuruta
CPC分类号： G06F7/535 , G06F7/5375
摘要： A divider unit is provided for a high-radix division using a partial remainder. A quotient digit selecting device selects one from all quotient digits obtainable under an applied radix based on the signs and the upper digit values of the divisor and the partial remainder represented in the two's complement representation or, alternatively, on the upper digit values of the divisor and the partial remainder represented in the redundant binary representation. A number of divisor's multiple generating devices each generate at least one of 0 and a value obtained by multiplying the divisor with 2.sup.j (j=integer). At least one adding and subtracting device provides at least three inputs to generate a first product corresponding to any desired multiple of the divisor by adding or subtracting the outputs from the multiple generating devices and to generate another partial remainder by adding or subtracting the first product with a second product corresponding to a value obtained by multiplying the partial remainder by the radix.
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