公开(公告)号：US20080254333A1

公开(公告)日：2008-10-16

申请号：US12100176

申请日：2008-04-09

申请人： Masato YOSHINO ,  Kentaro Matsunaga ,  Seiji Fujiwara ,  Hiroyuki Yamauchi ,  Shigeo Kasai

发明人： Masato YOSHINO ,  Kentaro Matsunaga ,  Seiji Fujiwara ,  Hiroyuki Yamauchi ,  Shigeo Kasai

IPC分类号： H01M8/10

CPC分类号： H01M8/1213 ,  C25B1/04 ,  C25B9/08 ,  H01M4/8885 ,  H01M4/92 ,  H01M4/921 ,  Y02E60/366

摘要： To provide a high-temperature steam electrolytic apparatus and method that steam can be used as a common gas between a hydrogen electrode and an oxygen electrode, and the steam can be electrolyzed efficiently while the electrodes of the electrochemical cell are suppressed from oxidative and reductive degradation. A steam electrolytic apparatus 10, comprising an electrochemical cell composed of an electrolyte containing a solid oxide mainly, a hydrogen electrode and an oxygen electrode; a steam supply portion 13 for supplying the electrochemical cell 11 with a gas containing steam as a main component; a hydrogen gas discharge portion 14 for discharging hydrogen generated by the hydrogen electrode by electrolysis of the steam; and an oxygen gas discharge portion 15 for discharging oxygen generated by the oxygen electrode by electrolysis of the steam, wherein the oxygen electrode contains a reduction-resistant material.

摘要翻译： 为了提供一种高温蒸汽电解设备和方法，可以将蒸汽用作氢电极和氧电极之间的普通气体，并且可以有效地电解蒸汽，同时抑制电化学电池的电极氧化还原降解 。 一种蒸汽电解装置10，包括由主要含有固体氧化物的电解质组成的电化学电池，氢电极和氧电极; 用于向电化学电池11供应含有蒸汽作为主要成分的气体的蒸汽供应部分13; 用于通过蒸汽电解来排出由氢电极产生的氢的氢气排出部分14; 以及氧气排出部15，用于通过蒸汽的电解来排出由氧电极产生的氧，其中氧电极含有还原性材料。

公开(公告)号：US08462540B2

公开(公告)日：2013-06-11

申请号：US13284532

申请日：2011-10-28

申请人： Meng-Fan Chang ,  Lai-Fu Chen ,  Jui-Jen Wu ,  Hiroyuki Yamauchi

发明人： Meng-Fan Chang ,  Lai-Fu Chen ,  Jui-Jen Wu ,  Hiroyuki Yamauchi

IPC分类号： G11C11/412

CPC分类号： G11C11/412

摘要： A static random access memory cell comprising a first inverter, a second inverter, a first transistor, a second transistor, and a third transistor. The first inverter is cross-coupled with the second inverter. The first transistor is connected with a write word line, a write bit line, and a first output node of the first inverter. The second transistor is connected with a complementary write bit line, the write word line, and a second output node of the second inverter. The third transistor is connected with a read bit line, a read word line, and the first input node of the first inverter to form a read port transistor, and a read port is formed. The read port transistor has a feature of asymmetric threshold voltage, and the read bit line swing can be expanded by the decrease of clamping current or the boosted read bit line.

摘要翻译： 一种静态随机存取存储单元，包括第一反相器，第二反相器，第一晶体管，第二晶体管和第三晶体管。 第一个反相器与第二个反相器交叉耦合。 第一晶体管与第一反相器的写字线，写位线和第一输出节点连接。 第二晶体管与第二反相器的互补写位线，写字线和第二输出节点连接。 第三晶体管与读位线，读字线和第一反相器的第一输入节点连接，形成读端口晶体管，形成读端口。 读端口晶体管具有不对称阈值电压的特征，并且可以通过钳位电流或升压读位线的减小来扩展读位线摆幅。

公开(公告)号：US07857227B2

公开(公告)日：2010-12-28

申请号：US11404786

申请日：2006-04-17

申请人： Yukio Masubuchi ,  Hiroyuki Yamauchi ,  Tomohiro Ono

发明人： Yukio Masubuchi ,  Hiroyuki Yamauchi ,  Tomohiro Ono

IPC分类号： G06K19/06

CPC分类号： G06K19/07345 ,  G06K19/0724 ,  G06K19/07767

摘要： A non-contact IC tag includes; a plurality of antennas corresponding to a plurality of frequency bands, and a peel-off sticker. The peel-off sticker is applied to at least one of the plurality of antennas and can be peeled off to disable the at least one antenna to which the peel-off sticker is applied.

摘要翻译： 非接触IC标签包括： 对应于多个频带的多个天线和剥离贴纸。 剥离贴纸被施加到多个天线中的至少一个天线，并且可以被剥离以禁用施加剥离贴纸的至少一个天线。

公开(公告)号：US20080067552A1

公开(公告)日：2008-03-20

申请号：US11980562

申请日：2007-10-31

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H01L27/11 ,  G06F17/50

CPC分类号： H01L27/11 ,  G06F17/5045 ,  G06F17/5068 ,  G06F2217/08 ,  G11C11/412 ,  H01L27/1104

摘要： A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.

摘要翻译： 半导体集成电路器件具有由形成在衬底上的电路元件或电线组成的多个设计图案。 根据每个设计图案的几何特征，多个设计图案的各个成品尺寸具有多个不同于一种设计图案的最小尺寸值。

公开(公告)号：US07218544B2

公开(公告)日：2007-05-15

申请号：US11121135

申请日：2005-05-04

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G11C17/00 ,  G11C5/06

CPC分类号： G11C17/12 ,  H01L27/112

摘要： A mask ROM includes bit lines, word lines intersecting with the bit lines and bit cells provided along the word lines, each of the bit lines being formed of a cell transistor having a gate connected to an associated one of the word lines. In the mask ROM, further provided is a source node commonly connected to respective sources of ones of the cell transistors having a gate connected to one of adjacent two word lines. A current flows from a selected bit line to a non-selected bit line via a cell transistor selected in reading out data and the source node.

摘要翻译： 掩模ROM包括位线，与位线相交的字线和沿着字线提供的位单元，每个位线由具有连接到相关联的字线之一的栅极的单元晶体管形成。 在掩模ROM中，进一步提供了一个源节点，其通常连接到具有连接到相邻两个字线中的一个的栅极的一个单元晶体管的各个源极。 A电流通过在读出数据和源节点中选择的单元晶体管从选定的位线流向未选择的位线。

公开(公告)号：US07146483B2

公开(公告)日：2006-12-05

申请号：US10329164

申请日：2002-12-24

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G06F12/00

CPC分类号： G06F12/0292 ,  G06F12/08

摘要： A memory system includes a memory including a plurality of memory regions operating based on an identical principle; and an address conversion device for converting a logical address into a physical address based on a correspondence between an address space and the plurality of memory regions. The correspondence is defined based on an inherent condition regarding a performance of the memory.

公开(公告)号：US06985007B2

公开(公告)日：2006-01-10

申请号：US10708235

申请日：2004-02-18

申请人： Hiroyuki Yamauchi ,  Tadahiro Yoshida

发明人： Hiroyuki Yamauchi ,  Tadahiro Yoshida

IPC分类号： H03K19/003

CPC分类号： H01P5/02

摘要： A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data line; and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.

摘要翻译： 根据本发明的信号发送/接收装置包括：发送装置，用于发送数据; 用于接收数据的接收装置; 用于发送数据的数据线; 以及用于发送用于确定数据线的电压的偏置电压的电源线，其中所述发送装置和所述接收装置通过所述数据线和所述供给线彼此连接，所述发送装置包括：驱动器电路，用于输出 数据到数据线; 以及偏置产生装置，用于产生所述偏置电压并将偏置电压输出到所述电源线，所述接收装置包括：终端电阻，连接到所述数据线; 以及用于检测来自数据线的数据的接收器电路，其中数据线经由终端电阻器连接到电源线。

公开(公告)号：US20050034093A1

公开(公告)日：2005-02-10

申请号：US10935094

申请日：2004-09-08

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G06F17/50 ,  G11C11/412 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8244 ,  H01L23/52 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/11 ,  G06F17/5045 ,  G06F17/5068 ,  G06F2217/08 ,  G11C11/412 ,  H01L27/1104

摘要： A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.

摘要翻译： 半导体集成电路器件具有由形成在衬底上的电路元件或电线组成的多个设计图案。 根据每个设计图案的几何特征，多个设计图案的各个成品尺寸具有多个不同于一种设计图案的最小尺寸值。

公开(公告)号：US06826074B2

公开(公告)日：2004-11-30

申请号：US10623691

申请日：2003-07-22

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G11C1100

CPC分类号： G11C7/12

摘要： In a semiconductor memory device, a precharge potential for non-selected bit lines among a plurality of bit lines, supplied by a HPR voltage source, is set at a value (for example, ½ Vcc=0.4 V) lower than the power supply voltage Vcc (low voltage in the range of 0.5 V to 1.2 V; for example, 0.8 V) determining the high-level side potential of data stored in a memory cell. A potential for non-selected word lines among a plurality of word lines, supplied by a NWL voltage source, is set at a predetermined negative potential (for example, −¼ Vcc=−0.2 V). The total of the precharge potential (0.4 V) of non-selected bit lines and the absolute value of the negative potential (−0.2 V) of non-selected word lines is set at a value less than the power supply voltage Vcc (0.8 V). By these settings, gate leakage current and GIDL current can be effectively limited to a small value while realizing effective limitation of OFF leakage current in a plurality of memory cells.

摘要翻译： 在半导体存储器件中，由HPR电压源提供的多个位线之中的未选位线的预充电电位被设定为比电源电压低的值（例如，½Vcc = 0.4V） Vcc（在0.5V至1.2V的范围内的低电压，例如0.8V）确定存储在存储单元中的数据的高电平侧电位。 由NWL电压源提供的多个字线中的未选字线的电位被设定为预定的负电位（例如，-¼Vcc = -0.2V）。 非选择位线的预充电电位（0.4V）和非选择字线的负电位（-0.2V）的绝对值的总和被设定为小于电源电压Vcc（0.8V ）。 通过这些设定，能够有效地将栅泄漏电流和GIDL电流限制在小的值，同时实现多个存储单元中的OFF漏电流的有效限制。

公开(公告)号：US06770940B2

公开(公告)日：2004-08-03

申请号：US10445807

申请日：2003-05-28

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/1104 ,  Y10S257/903

摘要： First to third logic circuits and first to third static random access memories (SRAMs) are formed on one chip. Power to the first and third logic circuits and their SRAMs is shut off as required, while power to the second logic circuit and its SRAM is kept supplied. The third SRAM has the largest memory capacity. The average channel width of the first to third SRAM cell arrays is set at a half or less of that of the other circuit blocks, and the channel impurity concentration of the second and third SRAM cell arrays, which operate at low speed, is set higher than that of the first SRAM cell array, which operates at high speed, by additional ion implantation. By these settings, MOS transistors of low threshold voltage (Vt) are provided for the first SRAM cell array, while MOS transistors of high Vt are provided for the second and third SRAM cell arrays for leakage reduction.

摘要翻译： 在一个芯片上形成第一到第三逻辑电路和第一至第三静态随机存取存储器（SRAM）。 对第一和​​第三逻辑电路及其SRAM的电源根据需要关闭，同时保持供给第二逻辑电路及其SRAM的电源。 第三个SRAM具有最大的存储容量。 将第一至第三SRAM单元阵列的平均通道宽度设置为其他电路块的平均通道宽度的一半或更小，并且将以低速工作的第二和第三SRAM单元阵列的沟道杂质浓度设置得更高 比通过额外的离子注入高速运行的第一个SRAM单元阵列的SRAM单元阵列。 通过这些设置，为第一SRAM单元阵列提供低阈值电压（Vt）的MOS晶体管，而为第二和第三SRAM单元阵列提供高Vt的MOS晶体管用于泄漏减少。