公开(公告)号：US08848419B2

公开(公告)日：2014-09-30

申请号：US13570305

申请日：2012-08-09

申请人： Jui-Jen Wu ,  Meng-Fan Chang

发明人： Jui-Jen Wu ,  Meng-Fan Chang

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C7/14 ,  G11C11/419

摘要： A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different resistances at logic states “0” and “1.” A reference bit line is coupled to the supply voltage through a comparison resistance value, especially a resistance between high and low resistance of the memory element in the two logic states. Voltages on the bit line and reference bit line ramp toward a switching threshold at rates related to the resistance values. The first line to discharge to switching threshold voltage sets the sense circuit latch.

摘要翻译： 数字存储元件具有用于读取存储在位单元中的值的读出电路锁存器。 在寻址字线之前，位线是预先充电的。 在读取操作期间，位线通过位逻辑状态“0”和“1”处具有不同电阻的位单元存储元件耦合到电源电压。参考位线通过比较电阻值耦合到电源电压 特别是在两个逻辑状态下存储元件的高电阻和低电阻之间的电阻。 在与电阻值相关的速率下，位线上的电压和参考位线斜坡转向切换阈值。 第一行放电到开关阈值电压设置感测电路锁存器。

公开(公告)号：US08829887B2

公开(公告)日：2014-09-09

申请号：US12896429

申请日：2010-10-01

申请人： Ming-Pin Chen ,  Meng-Fan Chang ,  Wei-Cheng Wu

发明人： Ming-Pin Chen ,  Meng-Fan Chang ,  Wei-Cheng Wu

IPC分类号： G01R31/28

CPC分类号： H03K21/023 ,  H03K21/026 ,  H03K21/38

摘要： A 3D-IC detector for each layer of a stacked device comprises a pulse generator to receive an initial signal and generate a pulse-in signal to a next stage detector. A latch is coupled to the pulse generator to receive an output signal from the pulse generator and generate a layer identifying signal. A counter is coupled to previous stage detector and the initial signal to perform a counting operation; and an adder coupled to the counter to add a number to a counting output from the counter and input added signal to the pulse generator.

摘要翻译： 用于层叠器件的每层的3D-IC检测器包括用于接收初始信号并向下一级检测器产生脉冲信号的脉冲发生器。 锁存器耦合到脉冲发生器以接收来自脉冲发生器的输出信号并产生层识别信号。 计数器耦合到前一级检测器和初始信号以执行计数操作; 以及加法器，其耦合到计数器以向计数器的计数输出添加数字，并将附加的信号输入到脉冲发生器。

公开(公告)号：US20130148402A1

公开(公告)日：2013-06-13

申请号：US13524980

申请日：2012-06-15

申请人： Meng-Fan CHANG ,  Wei-Cheng Wu ,  Tsung-Hsien Huang ,  Chien-Yuan Chen

发明人： Meng-Fan CHANG ,  Wei-Cheng Wu ,  Tsung-Hsien Huang ,  Chien-Yuan Chen

IPC分类号： G11C5/06

CPC分类号： G11C29/023 ,  G11C8/08 ,  G11C11/417 ,  G11C29/028 ,  G11C29/04 ,  G11C29/26 ,  G11C2029/1202 ,  G11C2029/1206 ,  G11C2029/2602

摘要： The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad.

摘要翻译： 本发明公开了一种包括主芯片和至少一个从芯片的3D存储器IC的控制方案。 主芯片包括主存储器核心，第一本地定时器，I / O缓冲器，第一焊盘和第二焊盘。 至少一个从芯片与主芯片堆叠。 每个从芯片包括从存储器核心，第二本地定时器和第三焊盘。 第一TSV耦合到第一焊盘和第三焊盘。 逻辑控制电路层包括逻辑控制电路和第四焊盘，逻辑控制电路耦合到第四焊盘。 第二TSV耦合到第二焊盘和第四焊盘。

公开(公告)号：US08390365B2

公开(公告)日：2013-03-05

申请号：US12906302

申请日：2010-10-18

申请人： Meng-Fan Chang ,  Shin-Jang Shen ,  Yi-Lun Lu

发明人： Meng-Fan Chang ,  Shin-Jang Shen ,  Yi-Lun Lu

IPC分类号： H02M3/00 ,  G05F3/08

CPC分类号： G11C7/222

摘要： A charge pump system for low-supply voltage includes: a clock generator to generate a plurality of clock signals; a clock pump circuit coupled to said clock generator to generate high voltage; a level shifter coupled to said clock generator and said clock pump circuit to generate a plurality of HV (high voltage) clock signals; a main pump circuit coupled to said clock generator and said level shifter to generate output voltage.

摘要翻译： 用于低电源电压的电荷泵系统包括：时钟发生器，用于产生多个时钟信号; 时钟泵电路，耦合到所述时钟发生器以产生高电压; 电平移位器，耦合到所述时钟发生器和所述时钟泵电路，以产生多个HV（高电压）时钟信号; 主泵电路耦合到所述时钟发生器和所述电平移位器以产生输出电压。

公开(公告)号：US20120092063A1

公开(公告)日：2012-04-19

申请号：US12906302

申请日：2010-10-18

申请人： Meng-Fan Chang ,  Shin-Jang Shen ,  Yi-Lun Lu

发明人： Meng-Fan Chang ,  Shin-Jang Shen ,  Yi-Lun Lu

IPC分类号： G05F3/02

CPC分类号： G11C7/222

摘要： The present invention discloses a charge pump system for low-supply voltage including: a clock generator to generate a plurality of clock signals; a clock pump circuit coupled to said clock generator to generate high voltage; a level shifter coupled to said clock generator and said clock pump circuit to generate a plurality of HV (high voltage)-clock signals; a main pump circuit coupled to said clock generator and said level shifter to generate output voltage.

摘要翻译： 本发明公开了一种用于低电源电压的电荷泵系统，包括：时钟发生器，用于产生多个时钟信号; 时钟泵电路，耦合到所述时钟发生器以产生高电压; 电平移位器，耦合到所述时钟发生器和所述时钟泵电路，以产生多个HV（高电压）时钟信号; 主泵电路耦合到所述时钟发生器和所述电平移位器以产生输出电压。

公开(公告)号：US08072244B1

公开(公告)日：2011-12-06

申请号：US12872004

申请日：2010-08-31

申请人： Chia-Chi Liu ,  Shin-Jang Shen ,  Meng-Fan Chang

发明人： Chia-Chi Liu ,  Shin-Jang Shen ,  Meng-Fan Chang

IPC分类号： G01R19/00

CPC分类号： G11C7/067 ,  G11C2207/063

摘要： The present invention relates to a current sensing amplifier and a method thereof. The current sensing amplifier comprises a first current path, a second current path, a first capacitor, a second capacitor and a latch circuit. When a first current and a second current flow in the first current path and the second current path respectively, the first and second capacitor may be charged by the first current and the second current. The first capacitor and the second capacitor may couple the charged voltage to the transistors in the first current path and the second current path when the first and second current path are cut off so as to cancel the effect of offset voltage of the transistors generated during the manufacturing process.

摘要翻译： 电流检测放大器及其方法技术领域本发明涉及一种电流检测放大器及其方法。 电流感测放大器包括第一电流路径，第二电流路径，第一电容器，第二电容器和锁存电路。 当第一电流和第二电流分别在第一电流路径和第二电流路径中流动时，第一和第二电容器可以由第一电流和第二电流充电。 当第一和第二电流路径被切断时，第一电容器和第二电容器可以将充电的电压耦合到第一电流路径中的晶体管和第二电流路径，以便消除在期间产生的晶体管的偏移电压的影响 制造工艺。

公开(公告)号：US08009498B2

公开(公告)日：2011-08-30

申请号：US12616910

申请日：2009-11-12

申请人： Meng-Fan Chang ,  Chih-Wen Cheng

发明人： Meng-Fan Chang ,  Chih-Wen Cheng

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2207/104 ,  G11C2211/4061

摘要： A memory refresh system includes a comparative detection circuit, a logic circuit, and a timing circuit. The comparative detection circuit detects a voltage of the storage capacitor of a memory cell of the memory and generates a corresponding digital code by comparing the voltage with a reference voltage. Each memory cell has a corresponding digital code. The combination of the digital codes of the memory cells forms a first state. After a specific period of time, the voltages of the storage capacitors of the memory cells are once detected by the comparative detection circuit, and corresponding digital codes are generated and combined to form a second state. The logic circuit compares the first state and the second state to determining whether or not to change the refresh period of a refresh period detecting process. The timing circuit changes the refresh period according to the determination result of the logic circuit.

摘要翻译： 存储器刷新系统包括比较检测电路，逻辑电路和定时电路。 比较检测电路检测存储器的存储单元的存储电容器的电压，并通过将电压与参考电压进行比较来产生相应的数字代码。 每个存储单元具有相应的数字代码。 存储器单元的数字代码的组合形成第一状态。 经过一定时间后，由比较检测电路一次检测存储单元的存储电容器的电压，生成并组合相应的数字代码形成第二状态。 逻辑电路比较第一状态和第二状态，以确定是否改变刷新周期检测处理的刷新周期。 定时电路根据逻辑电路的判定结果改变刷新周期。

公开(公告)号：US20110007568A1

公开(公告)日：2011-01-13

申请号：US12500236

申请日：2009-07-09

申请人： Meng-Fan Chang ,  Chih-Wei Liang ,  Chih-Chyuang Chiang

发明人： Meng-Fan Chang ,  Chih-Wei Liang ,  Chih-Chyuang Chiang

IPC分类号： G11C16/04

CPC分类号： G11C17/16 ,  G11C17/18

摘要： The invention discloses a NAND type ROM. The NAND type ROM comprises a plurality of bit lines, a plurality of word lines, a first source line, a second source line, and a plurality of NAND strings. The bit lines comprise a plurality of upper bit lines, first lower and second lower bit lines. The first lower and second lower bit lines are alternately arranged in parallel, and the plurality of word lines are vertically arranged to each bit lines. The first and second source line are respectively connected to the plurality of first and second lower bit lines. The plurality of NAND strings comprise a plurality of first and second NAND strings. The first NAND strings are connected to the upper bit lines, word lines, and first lower bit lines. The second NAND strings are connected to the upper bit lines, word lines, and second lower bit lines.

摘要翻译： 本发明公开了一种NAND型ROM。 NAND型ROM包括多个位线，多个字线，第一源极线，第二源极线和多个NAND串。 位线包括多个高位线，第一下位线和第二下位线。 第一下位线和第二下位线被并行交替排列，并且多个字线垂直地布置在每个位线上。 第一和第二源极线分别连接到多个第一和第二低位线。 多个NAND串包括多个第一和第二NAND串。 第一NAND串连接到高位线，字线和第一低位线。 第二NAND串连接到高位线，字线和第二低位线。

公开(公告)号：US20090273994A1

公开(公告)日：2009-11-05

申请号：US12403860

申请日：2009-03-13

申请人： MENG-FAN CHANG

发明人： MENG-FAN CHANG

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/227 ,  G11C11/413

摘要： A dual mode accessing signal control apparatus for being used in a dummy cells set of a memory, and a dual mode timing signal generating apparatus comprising a dual mode accessing signal control apparatus are provided. The dual mode accessing signal control apparatus respectively generates a write delay signal and a read signal during the write and the read process. The memory is thereby capable of self-timing its write and the read process, and is able to generate a wordline signal with a shorter width in the write process to ensure an early start to precharging. As a result, the whole duty period of the memory can be shortened.

摘要翻译： 提供了一种用于存储器的虚拟单元组的双模存取信号控制装置，以及包括双模存取信号控制装置的双模定时信号发生装置。 双模存取信号控制装置在写入和读取过程期间分别产生写延迟信号和读信号。 因此，存储器能够对其写入和读取过程进行自定时，并且能够在写入过程中产生具有较短宽度的字线信号，以确保早期开始预充电。 结果，可以缩短记忆的整个占空比。

公开(公告)号：US07289376B2

公开(公告)日：2007-10-30

申请号：US11201943

申请日：2005-08-10

申请人： Meng-Fan Chang ,  Kuei-Ann Wen

发明人： Meng-Fan Chang ,  Kuei-Ann Wen

IPC分类号： G11C7/10

CPC分类号： G11C17/14 ,  G11C7/02 ,  G11C7/12

摘要： The present invention provides a method for eliminating crosstalk (coupling noise) in a metal programmable read only memory. The metal programmable read only memory comprises a plurality of bit lines, a plurality of word lines, a plurality of precharge transistors, and a plurality of clamp transistors. When one of the bit lines is selected, bit lines adjacent to the selected bit line are fixed to a voltage value (VDD, GND or other voltages) by the clamp transistors. The clamping method can not cause voltage drops to the adjacent bit lines, and the crosstalk on the selected bit line can be eliminated simultaneously, so that the problem of read failures caused by the crosstalk in the high-speed metal programmable read only memory can be solved, and a higher speed can be reached.

摘要翻译： 本发明提供一种在金属可编程只读存储器中消除串扰（耦合噪声）的方法。 金属可编程只读存储器包括多个位线，多个字线，多个预充电晶体管和多个钳位晶体管。 当选择位线之一时，与所选位线相邻的位线被钳位晶体管固定为电压值（VDD，GND或其他电压）。 夹紧方法不会导致相邻位线的电压降，同时可以消除所选位线上的串扰，使得由高速金属可编程只读存储器中的串扰引起的读取故障的问题可以是 解决了，可以达到更高的速度。