公开(公告)号：US07339823B2

公开(公告)日：2008-03-04

申请号：US11544608

申请日：2006-10-10

申请人： Masayoshi Nakayama ,  Asako Miyoshi ,  Seiji Yamahira

发明人： Masayoshi Nakayama ,  Asako Miyoshi ,  Seiji Yamahira

IPC分类号： G11C11/34

CPC分类号： G11C16/32 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5641

摘要： A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses present in the memory cell at the same time are set to be different regions, a reading control circuit is constituted to carry out a reading operation by determining any of the divided regions which is to be read, selecting an optimum reading method and controlling the reading circuit based on the region information stored in the region information storage region, and an address which can be read in a short time in multivalued information stored in one memory cell is set to be a high speed reading region and is distinguished from regions having the other reading speeds. Consequently, it is possible to efficiently write and read information of 2 bits or more in one memory cell array without reducing a using efficiency of the memory cell array.

摘要翻译： 存储单元阵列在逻辑上被划分为具有不同读取速度的多个区域，具有不同读取速度的各个区域包括区域信息存储区域，用于存储其中同时存在于存储单元中的至少两个地址的区域信息 设置为不同的区域，读取控制电路被构成为通过确定要被读取的任何划分区域，选择最佳读取方法和基于存储在该区域中的区域信息来控制读取电路来执行读取操作 信息存储区域和在一个存储单元中存储的多值信息中可以在短时间内读取的地址被设置为高速读取区域，并且区别于具有其他读取速度的区域。 因此，可以在不降低存储单元阵列的使用效率的情况下有效地在一个存储单元阵列中写入和读取2位或更多的信息。

公开(公告)号：US20070086245A1

公开(公告)日：2007-04-19

申请号：US11544608

申请日：2006-10-10

申请人： Masayoshi Nakayama ,  Asako Miyoshi ,  Seiji Yamahira

发明人： Masayoshi Nakayama ,  Asako Miyoshi ,  Seiji Yamahira

IPC分类号： G11C16/04

CPC分类号： G11C16/32 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5641

摘要： A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses present in the memory cell at the same time are set to be different regions, a reading control circuit is constituted to carry out a reading operation by determining any of the divided regions which is to be read, selecting an optimum reading method and controlling the reading circuit based on the region information stored in the region information storage region, and an address which can be read in a short time in multivalued information stored in one memory cell is set to be a high speed reading region and is distinguished from regions having the other reading speeds. Consequently, it is possible to efficiently write and read information of 2 bits or more in one memory cell array without reducing a using efficiency of the memory cell array.

摘要翻译： 存储单元阵列在逻辑上被划分为具有不同读取速度的多个区域，具有不同读取速度的各个区域包括区域信息存储区域，用于存储其中同时存在于存储单元中的至少两个地址的区域信息 设置为不同的区域，读取控制电路被构成为通过确定要被读取的任何划分区域，选择最佳读取方法和基于存储在该区域中的区域信息来控制读取电路来执行读取操作 信息存储区域和在一个存储单元中存储的多值信息中可以在短时间内读取的地址被设置为高速读取区域，并且区别于具有其他读取速度的区域。 因此，可以在不降低存储单元阵列的使用效率的情况下有效地在一个存储单元阵列中写入和读取2位或更多的信息。

公开(公告)号：US07449918B2

公开(公告)日：2008-11-11

申请号：US11642965

申请日：2006-12-21

申请人： Seiji Yamahira ,  Toshiki Mori

发明人： Seiji Yamahira ,  Toshiki Mori

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： To provide a single-ended-output-type level shift circuit capable of improving an increase in a delay time according to a voltage level shift operation at low voltage and suppressing an increase in an area occupied by the circuit, first and second inverters 300 and 200 of a CMOS type in which a gate of each MOS transistor is individually driven are provided and the first inverter 300 is used as a level converting unit. A voltage level of a first control signal CS1 output from an output node no1 of the first inverter 300 is forcibly dropped down by a voltage dropping circuit CONT1 so as to accelerate the operation of the second inverter 200. As a result, the inversion of the level of an output signal of the first inverter 300 is accelerated. Further, the balance between current capabilities of the individual transistors is optimized and, in particular, the sizes of the transistors constituting the second inverter 200 are reduced so as to suppress an increase in a circuit area.

摘要翻译： 为了提供一种单端输出型电平移位电路，能够根据低电压电平移位操作改善延迟时间的增加，并抑制电路占用面积的增加，第一和第二逆变器300和 设置分别驱动每个MOS晶体管的栅极的CMOS型的200，并且将第一反相器300用作电平转换单元。 从第一反相器300的输出节点No1输出的第一控制信号CS1的电压电平被降压电路CONT 1强制降低，以加速第二反相器200的运行。 结果，第一逆变器300的输出信号的电平的反转加速。 此外，各个晶体管的电流能力之间的平衡被优化，特别地，构成第二反相器200的晶体管的尺寸减小，以抑制电路面积的增加。

公开(公告)号：US08319531B2

公开(公告)日：2012-11-27

申请号：US12902904

申请日：2010-10-12

申请人： Seiji Yamahira

发明人： Seiji Yamahira

IPC分类号： H03K21/00 ,  H03K23/00 ,  H03K25/00

CPC分类号： G06F1/06 ,  H03K5/135 ,  H03K5/15013 ,  H03K23/425

摘要： A divider circuit for dividing the frequency of a multi-phase clock signal, which can ensure a sufficient data latch time even if the multi-phase clock signal has a high frequency, includes a main latch circuit which generates an inverted data signal using, for example, two of eight clock signals of an eight-phase clock signal, and a sub-latch circuit which uses the eight clock signals as a trigger to receive the inverted data signal as a common data signal.

摘要翻译： 用于分割多相时钟信号的频率的分频电路，即使多相时钟信号具有高频率也能够确保足够的数据锁存时间，包括主锁存电路，其产生反相数据信号，用于 例如，八相时钟信号的八个时钟信号中的两个，以及使用八个时钟信号作为触发来接收反相数据信号作为公共数据信号的子锁存电路。

公开(公告)号：US08072258B2

公开(公告)日：2011-12-06

申请号：US12938108

申请日：2010-11-02

申请人： Seiji Yamahira

发明人： Seiji Yamahira

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/073 ,  H02M2003/077

摘要： In a booster circuit which is operated with a two-phase clock and in which a plurality of (M≧4) lines of boosting cells constitute a unit, a boosting cell in the K-th line (1≦K≦M) is controlled, depending on the voltage of the input terminal of a boosting cell in the KA-th line (KA=(K−1) when (K−1)>0, and KA=M when (K−1)=0). As a result, a charge transfer transistor can transition from the conductive state to the non-conductive state before a clock input to the boosting cell in the K-th line transitions from low to high and then boosting operation is performed. As a result, the backflow of charge via the charge transfer transistor can be reduced or prevented.

摘要翻译： 在以两相时钟进行操作的升压电路中，多个（M≥4）的升压电池单元构成单元的情况下，控制第K行（1＆amp; NlE; K＆nlE; M）中的升压单元 （K-1）> 0时KA =（K-1），（K-1）= 0时KA = M时，取决于KA线上的升压单元的输入端子的电压。 结果，在第K线的升压单元的时钟输入从低电平变为高电平之前，电荷转移晶体管可以从导通状态转变为非导通状态，然后执行升压操作。 结果，可以减少或防止经由电荷转移晶体管的电荷回流。

公开(公告)号：US07924086B2

公开(公告)日：2011-04-12

申请号：US12370057

申请日：2009-02-12

申请人： Seiji Yamahira

发明人： Seiji Yamahira

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/073 ,  H02M2003/075

摘要： A boosting circuit configuration with high boosting efficiency is provided which is based on a boosting circuit that performs an operation in accordance with a two-phase clock and which includes a plurality (M≧4) of boosting cell sequences (units). A boosting cell in a K-th sequence (1≦K≦M) is controlled, depending on the potential of the output terminal of a boosting cell in a KA-th sequence (KA=(K−1) when (K−1)>0, and KA=M when (K−1)=0). Thereby, before a clock input to the boosting cell in the K-th sequence goes from “L” to “H”, so that boosting is performed, a charge transfer transistor can be caused to go from the conductive state to the non-conductive state, so that a backflow of charges via charge transfer transistor can be prevented.

摘要翻译： 提供了一种具有高升压效率的升压电路结构，其基于升压电路，其执行根据两相时钟的操作，并且包括多个（M≥4）升压单元序列（单元）。 根据第KA次序列中的升压电池的输出端子的电位（KA =（K-1）），当K-1（K-1）时，第K个序列（1＆amp; NlE; K＆ ）> 0，KA = M时（K-1）= 0）。 因此，在第K个序列中的升压单元的时钟输入从“L”变为“H”之前，进行升压，可以使电荷转移晶体管从导通状态变为非导通状态 状态，从而可以防止通过电荷转移晶体管的电荷回流。

公开(公告)号：US07777557B2

公开(公告)日：2010-08-17

申请号：US12015882

申请日：2008-01-17

申请人： Seiji Yamahira

发明人： Seiji Yamahira

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  H02M3/073 ,  H02M2003/075

摘要： A boosting circuit comprises a first boosting cell row and a second boosting cell row. The boosting circuit further comprises an analog comparison circuit for comparing the potential of boosting cells on the same stage, and selecting and outputting the lower or higher of the potentials. The potential of an N well is controlled using the output potential of the analog comparison circuit. Thereby, the amplitude of an N well potential can be suppressed, and a single N well region can be shared.

摘要翻译： 升压电路包括第一升压单元行和第二升压单元行。 升压电路还包括用于比较同一级上的升压电池的电位以及选择和输出较低或更高电位的模拟比较电路。 使用模拟比较电路的输出电位来控制N阱的电位。 由此，能够抑制N阱电位的振幅，能够共享单个N阱区域。

公开(公告)号：US20100007408A1

公开(公告)日：2010-01-14

申请号：US12497090

申请日：2009-07-02

申请人： Seiji Yamahira

发明人： Seiji Yamahira

IPC分类号： G05F1/10

CPC分类号： G11C16/30 ,  G11C5/143 ,  G11C5/145

摘要： An output terminal of a first boost circuit is connected to a second boost circuit. After the second boost circuit is started up, a boost clock frequency of the second boost circuit is reduced. A time required to start up the second boost circuit is reduced, and in addition, a current supply capability of the first boost circuit is increased after the second boost circuit is started up. When the second boost circuit is driven, output voltages of the first and second boost circuits are stably supplied without instantaneously changing the output voltage of the first boost circuit.

摘要翻译： 第一升压电路的输出端子连接到第二升压电路。 在第二升压电路启动之后，第二升压电路的升压时钟频率降低。 降低启动第二升压电路所需的时间，此外，在第二升压电路启动之后，第一升压电路的电流供应能力增加。 当驱动第二升压电路时，稳定地提供第一和第二升压电路的输出电压，而不瞬时改变第一升压电路的输出电压。

公开(公告)号：US20070043984A1

公开(公告)日：2007-02-22

申请号：US11410051

申请日：2006-04-25

申请人： Toshiki Mori ,  Seiji Yamahira

发明人： Toshiki Mori ,  Seiji Yamahira

IPC分类号： G11C29/00

CPC分类号： G11C16/0483 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/3459

摘要： The nonvolatile semiconductor memory device includes: a first memory block having a first program level and a first read circuit; a second memory block having a second program level different from the first program level and a second read circuit of a scheme different from the first read circuit, the second memory block being formed on the same substrate as the first memory block; and a data output circuit for selecting either the first read circuit or the second read circuit and outputting data read via the selected read circuit externally.

摘要翻译： 非易失性半导体存储器件包括：具有第一编程电平和第一读取电路的第一存储器块; 具有与第一编程电平不同的第二编程电平的第二存储器块和与第一读取电路不同的方案的第二读取电路，第二存储器块形成在与第一存储器块相同的衬底上; 以及数据输出电路，用于选择第一读取电路或第二读取电路，并且从外部输出经由所选择的读取电路读取的数据。

公开(公告)号：US06914474B2

公开(公告)日：2005-07-05

申请号：US10731640

申请日：2003-12-10

申请人： Seiji Yamahira

发明人： Seiji Yamahira

IPC分类号： G11C16/06 ,  G05F3/26 ,  G05F3/02

CPC分类号： G05F3/262

摘要： To provide a voltage generating circuit for generating a boosted voltage on the basis of a power source voltage or any voltage.A voltage generating circuit having a boosting circuit 1 for generating a voltage higher than a power source voltage, and a reference voltage generating circuit 2 for generating a reference voltage Vref is equipped with a voltage variation detecting circuit 4 having a first input connected to the output of the boosting circuit 1, a second input having a power source Vdd and a third input connected to the ground Vss, a control voltage Vfd being generated at a first output by making reference current equivalent to current occurring due to the potential difference between the first input and the second input flow into the third input, a differential amplifier circuit 61 for comparing the control voltage Vfd and the reference voltage Vref, and a clamp circuit 62 for extracting current from the output of the boosting circuit 1 in accordance with the output of the differential amplifier circuit 61, thereby controlling the output voltage of the boosting circuit 1.

摘要翻译： 提供用于基于电源电压或任何电压产生升压电压的电压产生电路。 具有用于产生高于电源电压的电压的升压电路1的电压产生电路和用于产生参考电压Vref的参考电压产生电路2配备有电压变化检测电路4，其具有连接到输出端的第一输入端 升压电路1的第二输入端，具有与源极Vss连接的电源Vdd和第三输入端的第二输入端，通过使与第一输出端子之间的电位差产生的电流相当的参考电流等于在第一输出端产生的控制电压Vfd 输入和第二输入流入第三输入端，用于比较控制电压Vfd和参考电压Vref的差分放大器电路61和用于根据升压电路1的输出从升压电路1的输出提取电流的钳位电路62 差分放大电路61，从而控制升压电路1的输出电压。