公开(公告)号：US20070043984A1

公开(公告)日：2007-02-22

申请号：US11410051

申请日：2006-04-25

申请人： Toshiki Mori ,  Seiji Yamahira

发明人： Toshiki Mori ,  Seiji Yamahira

IPC分类号： G11C29/00

CPC分类号： G11C16/0483 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/3459

摘要： The nonvolatile semiconductor memory device includes: a first memory block having a first program level and a first read circuit; a second memory block having a second program level different from the first program level and a second read circuit of a scheme different from the first read circuit, the second memory block being formed on the same substrate as the first memory block; and a data output circuit for selecting either the first read circuit or the second read circuit and outputting data read via the selected read circuit externally.

摘要翻译： 非易失性半导体存储器件包括：具有第一编程电平和第一读取电路的第一存储器块; 具有与第一编程电平不同的第二编程电平的第二存储器块和与第一读取电路不同的方案的第二读取电路，第二存储器块形成在与第一存储器块相同的衬底上; 以及数据输出电路，用于选择第一读取电路或第二读取电路，并且从外部输出经由所选择的读取电路读取的数据。

公开(公告)号：US07449918B2

公开(公告)日：2008-11-11

申请号：US11642965

申请日：2006-12-21

申请人： Seiji Yamahira ,  Toshiki Mori

发明人： Seiji Yamahira ,  Toshiki Mori

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： To provide a single-ended-output-type level shift circuit capable of improving an increase in a delay time according to a voltage level shift operation at low voltage and suppressing an increase in an area occupied by the circuit, first and second inverters 300 and 200 of a CMOS type in which a gate of each MOS transistor is individually driven are provided and the first inverter 300 is used as a level converting unit. A voltage level of a first control signal CS1 output from an output node no1 of the first inverter 300 is forcibly dropped down by a voltage dropping circuit CONT1 so as to accelerate the operation of the second inverter 200. As a result, the inversion of the level of an output signal of the first inverter 300 is accelerated. Further, the balance between current capabilities of the individual transistors is optimized and, in particular, the sizes of the transistors constituting the second inverter 200 are reduced so as to suppress an increase in a circuit area.

摘要翻译： 为了提供一种单端输出型电平移位电路，能够根据低电压电平移位操作改善延迟时间的增加，并抑制电路占用面积的增加，第一和第二逆变器300和 设置分别驱动每个MOS晶体管的栅极的CMOS型的200，并且将第一反相器300用作电平转换单元。 从第一反相器300的输出节点No1输出的第一控制信号CS1的电压电平被降压电路CONT 1强制降低，以加速第二反相器200的运行。 结果，第一逆变器300的输出信号的电平的反转加速。 此外，各个晶体管的电流能力之间的平衡被优化，特别地，构成第二反相器200的晶体管的尺寸减小，以抑制电路面积的增加。

公开(公告)号：US07511559B2

公开(公告)日：2009-03-31

申请号：US11643696

申请日：2006-12-22

申请人： Seiji Yamahira ,  Toshiki Mori

发明人： Seiji Yamahira ,  Toshiki Mori

IPC分类号： G05F1/10

CPC分类号： H02M3/073 ,  H02M2003/075

摘要： A pull-out lower limit voltage for setting a voltage level when the gate voltage of the charge transfer transistor is pulled out is supplied to a reset circuit. In order to secure the breakdown voltage margin of the transistor and the capacitor used in a booster cell, a voltage which is not necessarily constant is used as the pull-out lower limit voltage. Accordingly, it is possible to provide a stabilized booster circuit in which an optimal gate voltage level of the charge transfer transistor can be set, overcharging can be suppressed, and the recovery time of the booster circuit can be shortened.

摘要翻译： 当拉出电荷转移晶体管的栅极电压时，用于设定电压电平的拉出下限电压被提供给复位电路。 为了确保升压电池中使用的晶体管和电容器的击穿电压裕度，不一定是恒定的电压用作拉出下限电压。 因此，可以提供稳定的升压电路，其中可以设置电荷转移晶体管的最佳栅极电压电平，可以抑制过充电，并且可以缩短升压电路的恢复时间。

公开(公告)号：US20070146054A1

公开(公告)日：2007-06-28

申请号：US11643696

申请日：2006-12-22

申请人： Seiji Yamahira ,  Toshiki Mori

发明人： Seiji Yamahira ,  Toshiki Mori

IPC分类号： G05F1/10

CPC分类号： H02M3/073 ,  H02M2003/075

摘要： A pull-out lower limit voltage for setting a voltage level when the gate voltage of the charge transfer transistor is pulled out is supplied to a reset circuit. In order to secure the breakdown voltage margin of the transistor and the capacitor used in a booster cell, a voltage which is not necessarily constant is used as the pull-out lower limit voltage. Accordingly, it is possible to provide a stabilized booster circuit in which an optimal gate voltage level of the charge transfer transistor can be set, overcharging can be suppressed, and the recovery time of the booster circuit can be shortened.

摘要翻译： 当拉出电荷转移晶体管的栅极电压时，用于设定电压电平的拉出下限电压被提供给复位电路。 为了确保升压电池中使用的晶体管和电容器的击穿电压裕度，不一定是恒定的电压用作拉出下限电压。 因此，可以提供稳定的升压电路，其中可以设置电荷转移晶体管的最佳栅极电压电平，可以抑制过充电，并且可以缩短升压电路的恢复时间。

公开(公告)号：US20070188192A1

公开(公告)日：2007-08-16

申请号：US11642965

申请日：2006-12-21

申请人： Seiji Yamahira ,  Toshiki Mori

发明人： Seiji Yamahira ,  Toshiki Mori

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： To provide a single-ended-output-type level shift circuit capable of improving an increase in a delay time according to a voltage level shift operation at low voltage and suppressing an increase in an area occupied by the circuit, first and second inverters 300 and 200 of a CMOS type in which a gate of each MOS transistor is individually driven are provided and the first inverter 300 is used as a level converting unit. A voltage level of a first control signal CS1 output from an output node no1 of the first inverter 300 is forcibly dropped down by a voltage dropping circuit CONT1 so as to accelerate the operation of the second inverter 200. As a result, the inversion of the level of an output signal of the first inverter 300 is accelerated. Further, the balance between current capabilities of the individual transistors is optimized and, in particular, the sizes of the transistors constituting the second inverter 200 are reduced so as to suppress an increase in a circuit area.

摘要翻译： 为了提供一种单端输出型电平移位电路，能够根据低电压电平移位操作改善延迟时间的增加，并抑制电路占用面积的增加，第一和第二逆变器300和 设置分别驱动每个MOS晶体管的栅极的CMOS型的200，并且将第一反相器300用作电平转换单元。 从第一逆变器300的输出节点no1输出的第一控制信号CS1的电压电平被降压电路CONT 1强制下降，以加速第二反相器200的运行。 结果，第一逆变器300的输出信号的电平的反转加速。 此外，各个晶体管的电流能力之间的平衡被优化，特别地，构成第二反相器200的晶体管的尺寸减小，以抑制电路面积的增加。

公开(公告)号：US08977103B2

公开(公告)日：2015-03-10

申请号：US12507565

申请日：2009-07-22

申请人： Toshiki Mori ,  Yoshiro Osaki ,  Naoko Satoh ,  Kiyoshi Yamaguchi ,  Yasuyuki Ushio ,  Kenji Kimiyama

发明人： Toshiki Mori ,  Yoshiro Osaki ,  Naoko Satoh ,  Kiyoshi Yamaguchi ,  Yasuyuki Ushio ,  Kenji Kimiyama

IPC分类号： H04N5/92 ,  G11B27/32 ,  G11B27/10 ,  G11B27/30 ,  G11B27/34 ,  H04N21/845 ,  H04N5/44

CPC分类号： G11B27/329 ,  G11B27/105 ,  G11B27/3027 ,  G11B27/34 ,  G11B2220/61 ,  H04N5/4403 ,  H04N21/42692 ,  H04N21/4325 ,  H04N21/47217 ,  H04N21/482 ,  H04N21/8455 ,  H04N21/8456

摘要： A video data processing apparatus includes a reading unit reading video data from a video data file recorded on a randomly accessible storage medium in response to a first control signal, and reading position data indicating a frame position of the video data in the video data file from the video data file recorded on the storage medium in response to a second control signal, a memory storing the position data read by the reading unit, and a controller controlling the reading unit by outputting the second control signal before the outputting of the first control signal, and controlling the reading unit by outputting the first control signal with a designation of particular video data to be read indicated by the position data stored in the memory, in response to a request to execute a process to the video data file.

摘要翻译： 视频数据处理装置包括：读取单元，响应于第一控制信号从记录在随机存取的存储介质上的视频数据文件读取视频数据;以及读取指示视频数据文件中的视频数据的帧位置的位置数据， 响应于第二控制信号记录在存储介质上的视频数据文件，存储由读取单元读取的位置数据的存储器和控制读取单元的控制器，在输出第一控制信号之前输出第二控制信号 响应于执行对视频数据文件的处理的请求，通过输出具有由存储在存储器中的位置数据指示的特定视频数据的指定的第一控制信号来控制读取单元。

公开(公告)号：US08750481B2

公开(公告)日：2014-06-10

申请号：US11216052

申请日：2005-09-01

申请人： Yoshiro Osaki ,  Toshiki Mori

发明人： Yoshiro Osaki ,  Toshiki Mori

IPC分类号： H04M11/00

CPC分类号： H04L12/66

摘要： A telephone system comprising a plurality of phone devices and a plurality of information terminals for mutually communicating via a communication network, comprising position managing means for managing mutual position relations between the plurality of phone devices and the plurality of information terminals, and correlating means for mutually correlating at 1:1 between the plurality of phone devices and the plurality of information terminals on the basis of the managed position relations.

摘要翻译： 一种电话系统，包括多个电话设备和用于经由通信网络相互通信的多个信息终端，包括用于管理所述多个电话设备与所述多个信息终端之间的相互位置关系的位置管理装置，以及用于相互通信的相关装置 基于管理的位置关系，在多个电话装置与多个信息终端之间以1：1关联。

公开(公告)号：US07706194B2

公开(公告)日：2010-04-27

申请号：US12108948

申请日：2008-04-24

申请人： Toshiki Mori

发明人： Toshiki Mori

IPC分类号： G11C5/14

CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C8/10 ,  G11C16/10

摘要： A semiconductor memory device includes: a memory cell array including a plurality of memory cells arranged in rows and columns for holding information, each of the memory cells having a control gate; a plurality of word lines extending in a row direction, each of the word lines being connected to the control gates of the memory cells of a corresponding row of the memory cell array; a plurality of bit lines extending in a column direction and connected to sources or drains of the memory cells; a row decoder for selecting any of the plurality of word lines; a column decoder for selecting any of the plurality of bit lines; a charge pump circuit for generating a voltage higher than a supply voltage; and a first switch located in a connection path between the row decoder and the charge pump circuit.

摘要翻译： 半导体存储器件包括：存储单元阵列，包括以行和列排列的用于保持信息的多个存储器单元，每个存储器单元具有控制栅极; 沿行方向延伸的多个字线，每条字线连接到存储单元阵列的对应行的存储单元的控制栅极; 沿列方向延伸并连接到存储单元的源极或漏极的多个位线; 行解码器，用于选择多个字线中的任一个; 列解码器，用于选择多个位线中的任一个; 用于产生高于电源电压的电压的电荷泵电路; 以及位于行解码器和电荷泵电路之间的连接路径中的第一开关。

公开(公告)号：US07689449B1

公开(公告)日：2010-03-30

申请号：US09487265

申请日：2000-01-19

申请人： Toshiki Mori ,  Minoru Kuriki ,  Yasuyuki Jinbo ,  Kiyoto Naganuma ,  Masao Aihara

发明人： Toshiki Mori ,  Minoru Kuriki ,  Yasuyuki Jinbo ,  Kiyoto Naganuma ,  Masao Aihara

IPC分类号： G06Q99/00

CPC分类号： G06Q10/063116 ,  G06Q10/10 ,  H04L51/34

摘要： It is determined whether or not a transmitter has issued a request to display a completion state table, whether or not the current date and time have reached the date and time specified by the transmitter, whether or not an opening rate has exceeded a predetermined value, or whether or not a completion rate has exceeded a predetermined value. When any of these conditions is satisfied, a completion state table containing information such as the number of receivers who have opened the message, the opening rate, the number of receivers who have completed their jobs associated with the message, the completion rate, etc. is forcibly displayed on a terminal device.

摘要翻译： 确定发射机是否已经发出显示完成状态表的请求，无论当前日期和时间是否已经达到由发射机指定的日期和时间，开启率是否超过预定值， 或者完成率是否超过预定值。 当满足这些条件中的任何一个时，包含已经打开消息的接收者的数量，打开率，完成与消息相关联的接收者的数量，完成率等的信息的完成状态表。 被强制显示在终端设备上。

公开(公告)号：US20100031001A1

公开(公告)日：2010-02-04

申请号：US12487170

申请日：2009-06-18

申请人： Masahiro Ueminami ,  Kazuyo Nishikawa ,  Masahiro Kuramochi ,  Tadashi Nitta ,  Toshiki Mori

发明人： Masahiro Ueminami ,  Kazuyo Nishikawa ,  Masahiro Kuramochi ,  Tadashi Nitta ,  Toshiki Mori

IPC分类号： G06F12/06

CPC分类号： G11C5/066 ,  G11C7/10 ,  G11C16/10 ,  G11C2216/30

摘要： In a serial memory device which performs reception and transmission of command, address, and data via serial communication with a host controller, a base address holding circuit holds a base address which serves as a base for effective address calculation. An address operation circuit calculates an effective address based on the base address and an address input from the host controller.

摘要翻译： 在通过与主机控制器的串行通信来执行命令，地址和数据的接收和发送的串行存储器件中，基地址保持电路保持用作有效地址计算的基础的基地址。 地址运算电路根据基地址和从主机控制器输入的地址来计算有效地址。