公开(公告)号：US20120166774A1

公开(公告)日：2012-06-28

申请号：US13281074

申请日：2011-10-25

申请人： Masayuki TSUJI

发明人： Masayuki TSUJI

IPC分类号： G06F9/30

CPC分类号： G06F9/3867 ,  G06F9/3861 ,  G06F11/2236

摘要： A non-transitory computer-readable medium storing a processor testing program causing a computer to execute a testing process for a processor, the processor having a plurality of pipeline stages for processing an instruction and a controller for providing the pipeline stage with an inter-lock signal for aborting a transition of the instruction between the pipeline stages when a pipeline hazard is expected to occur. The testing process has a timing generating process including: referring to a pipeline-stage combination pattern indicating whether or not an instruction is under process at each pipeline stage and prescribes a processing status to be tested, and timing generating which provides the inter-lock signal, while an instruction included in a test instruction sequence is executed, so that a processing status of the instruction is matched with the processing status to be tested according to an status information.

摘要翻译： 一种非暂时的计算机可读介质，其存储处理器测试程序，使计算机执行处理器的测试过程，所述处理器具有用于处理指令的多个流水线级，以及用于向所述流水线级提供锁相 当期望发生管道危险时，用于中止流水线阶段之间的指令转换的信号。 测试过程具有定时生成处理，其包括：参考指示每个流水线阶段是否正在处理指令的流水线级组合模式，并规定要测试的处理状态，以及提供锁相信号的定时生成 同时执行包含在测试指令序列中的指令，使得指令的处理状态与待测试的处理状态根据状态信息相匹配。

公开(公告)号：US20110289298A1

公开(公告)日：2011-11-24

申请号：US13028840

申请日：2011-02-16

申请人： Masayuki TSUJI

发明人： Masayuki TSUJI

IPC分类号： G06F9/30

CPC分类号： G06F9/3877 ,  G06F9/3881

摘要： A semiconductor circuit includes a memory which stores data; a processing device which executes a program, writes argument data of a function of the program into the memory referring to an address stored in a stack pointer, when a value of a program counter, which indicates an address of the program under execution, reaches a hardware accelerator starting address, and outputs the address stored in the stack pointer; and a hardware accelerator which receives the address of the stack pointer from the processing device, when a value of the program counter of the processing device reaches the hardware accelerator starting address, reads the argument data of the function from the memory referring to the address stored in the stack pointer, and executes the function implemented in hardware using the argument data.

摘要翻译： 半导体电路包括存储数据的存储器; 执行程序的处理装置，当指示正在执行的程序的地址的程序计数器的值到达时，将参考存储在堆栈指针中的地址的程序的功能的参数数据写入存储器 硬件加速器起始地址，并输出存储在堆栈指针中的地址; 以及硬件加速器，当处理装置的程序计数器的值达到硬件加速器开始地址时，从处理装置接收堆栈指针的地址，参考所存储的地址从存储器读取该功能的参数数据 在堆栈指针中，并使用参数数据执行在硬件中实现的功能。

公开(公告)号：US20100318766A1

公开(公告)日：2010-12-16

申请号：US12795478

申请日：2010-06-07

申请人： Masayuki TSUJI

发明人： Masayuki TSUJI

IPC分类号： G06F15/76 ,  G06F9/02

CPC分类号： G06F9/3887 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30141

摘要： A processor includes a processing unit capable of executing single-instruction multiple-data operations; a register file configured to store data that is to be supplied to the processing unit and to be subjected to operations, and a buffer provided separately from the register file, the buffer being a buffer where an integer “n” number of data columns each having a plurality of data elements are written on a column-by-column basis, and data elements at the same location are selected and read as “n” data elements from the respective “n” data columns, wherein the “n” data elements read from the buffer is supplied to the processing unit as data to be subjected to a single-instruction multiple-data operation.

摘要翻译： 处理器包括能够执行单指令多数据操作的处理单元; 配置为存储要提供给处理单元并进行操作的数据的寄存器文件以及与寄存器文件分开设置的缓冲器，该缓冲器是整数“n”个数据列的缓冲器，每个数据列具有 多个数据元素被逐列地写入，并且相同位置的数据元素被选择并从相应的“n”个数据列读取为“n”个数据元素，其中“n”个数据元素被读取 从缓冲器被提供给处理单元作为要进行单指令多数据操作的数据。

公开(公告)号：US20090195738A1

公开(公告)日：2009-08-06

申请号：US12420836

申请日：2009-04-09

申请人： Naoshi YAMADA ,  Hidehiko YAMAGUCHI ,  Toshihide TSUBATA ,  Yukio KUROZUMI ,  Masayuki TSUJI

发明人： Naoshi YAMADA ,  Hidehiko YAMAGUCHI ,  Toshihide TSUBATA ,  Yukio KUROZUMI ,  Masayuki TSUJI

IPC分类号： G02F1/1339 ,  G02F1/1333

CPC分类号： G02F1/1339 ,  G02F1/133351 ,  G02F2001/13415

摘要： The method of the present invention includes the steps of: (A) providing a first substrate, and a second substrate, wherein the first substrate includes a first light shielding layer provided within a non-display region, the first light shielding layer including a light-transmitting portion provided near an outer boundary of the first light shielding layer, the light-transmitting portion comprising a recess or an opening; (B) drawing a seal pattern with a sealant, the seal pattern being drawn outside the first light shielding layer so as to surround the display region, comprising the substeps of: (B1) beginning application of the sealant near the light-transmitting portion, (B2) applying the sealant along an outer periphery of the first light shielding layer, and (B3) forming a junction with the sealant having been applied near the light-transmitting portion; (C) applying a liquid crystal material within the display region surrounded by the sealant; (D) attaching the first substrate and the second substrate; and (E) performing light irradiation from the first substrate side to cure the sealant.

摘要翻译： 本发明的方法包括以下步骤：（A）提供第一衬底和第二衬底，其中第一衬底包括设置在非显示区域内的第一遮光层，第一遮光层包括光 所述发光部分设置在所述第一遮光层的外边界附近，所述光透射部分包括凹部或开口; （B）利用密封剂来绘制密封图案，密封图案被拉出到第一遮光层的外面以包围显示区域，包括以下子步骤：（B1）开始在透光部分附近施加密封剂， （B2）沿着所述第一遮光层的外周施加所述密封剂，和（B3）与所述密封剂形成与所述透光部附近的接合部; （C）在由密封剂包围的显示区域内施加液晶材料; （D）连接第一基板和第二基板; 和（E）从第一基板侧执行光照射以固化密封剂。

公开(公告)号：US20110051069A1

公开(公告)日：2011-03-03

申请号：US12942185

申请日：2010-11-09

申请人： Naoshi YAMADA ,  Hidehiko YAMAGUCHI ,  Toshihide TSUBATA ,  Yukio KUROZUMI ,  Masayuki TSUJI

发明人： Naoshi YAMADA ,  Hidehiko YAMAGUCHI ,  Toshihide TSUBATA ,  Yukio KUROZUMI ,  Masayuki TSUJI

IPC分类号： G02F1/1339

CPC分类号： G02F1/1339 ,  G02F1/133351 ,  G02F2001/13415

摘要： The method of the present invention includes the steps of (A) providing a first substrate, and a second substrate, wherein the first substrate includes a first light shielding layer provided within a non-display region, the first light shielding layer including a light-transmitting portion provided near an outer boundary of the first light shielding layer, the light-transmitting portion comprising a recess or an opening; (B) drawing a seal pattern with a sealant, the seal pattern being drawn outside the first light shielding layer so as to surround the display region, comprising the substeps of: (B1) beginning application of the sealant near the light-transmitting portion, (B2) applying the sealant along an outer periphery of the first light shielding layer, and (B3) forming a junction with the sealant having been applied near the light-transmitting portion; (C) applying a liquid crystal material within the display region surrounded by the sealant; (D) attaching the first substrate and the second substrate; and (E) performing light irradiation from the first substrate side to cure the sealant.

摘要翻译： 本发明的方法包括以下步骤：（A）提供第一衬底和第二衬底，其中第一衬底包括设置在非显示区域内的第一遮光层，第一遮光层包括发光层， 所述透光部设置在所述第一遮光层的外边界附近，所述透光部包括凹部或开口; （B）利用密封剂来绘制密封图案，密封图案被拉出到第一遮光层的外面以包围显示区域，包括以下子步骤：（B1）开始在透光部分附近施加密封剂， （B2）沿着所述第一遮光层的外周施加所述密封剂，和（B3）与所述密封剂形成与所述透光部附近的接合部; （C）在由密封剂包围的显示区域内施加液晶材料; （D）连接第一基板和第二基板; 和（E）从第一基板侧执行光照射以固化密封剂。

公开(公告)号：US20100277683A1

公开(公告)日：2010-11-04

申请号：US12835067

申请日：2010-07-13

申请人： Naoshi YAMADA ,  Hidehiko YAMAGUCHI ,  Toshihide TSUBATA ,  Yukio KUROZUMI ,  Masayuki TSUJI

发明人： Naoshi YAMADA ,  Hidehiko YAMAGUCHI ,  Toshihide TSUBATA ,  Yukio KUROZUMI ,  Masayuki TSUJI

IPC分类号： G02F1/1339

CPC分类号： G02F1/1339 ,  G02F1/133351 ,  G02F2001/13415

摘要： The method of the present invention includes the steps of: (A) providing a first substrate, and a second substrate, wherein the first substrate includes a first light shielding layer provided within a non-display region, the first light shielding layer including a light-transmitting portion provided near an outer boundary of the first light shielding layer, the light-transmitting portion comprising a recess or an opening; (B) drawing a seal pattern with a sealant, the seal pattern being drawn outside the first light shielding layer so as to surround the display region, comprising the substeps of: (B1) beginning application of the sealant near the light-transmitting portion, (B2) applying the sealant along an outer periphery of the first light shielding layer, and (B3) forming a junction with the sealant having been applied near the light-transmitting portion; (C) applying a liquid crystal material within the display region surrounded by the sealant; (D) attaching the first substrate and the second substrate; and (E) performing light irradiation from the first substrate side to cure the sealant.

摘要翻译： 本发明的方法包括以下步骤：（A）提供第一衬底和第二衬底，其中第一衬底包括设置在非显示区域内的第一遮光层，第一遮光层包括光 所述发光部分设置在所述第一遮光层的外边界附近，所述光透射部分包括凹部或开口; （B）利用密封剂来绘制密封图案，密封图案被拉出到第一遮光层的外面以包围显示区域，包括以下子步骤：（B1）开始在透光部分附近施加密封剂， （B2）沿着所述第一遮光层的外周施加所述密封剂，和（B3）与所述密封剂形成与所述透光部附近的接合部; （C）在由密封剂包围的显示区域内施加液晶材料; （D）连接第一基板和第二基板; 和（E）从第一基板侧执行光照射以固化密封剂。

公开(公告)号：US20100169889A1

公开(公告)日：2010-07-01

申请号：US12624105

申请日：2009-11-23

申请人： Masayuki TSUJI

发明人： Masayuki TSUJI

IPC分类号： G06F9/46 ,  G06F15/76 ,  G06F9/02

CPC分类号： G06F15/16 ,  G06F9/3828 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/52

摘要： A multi-core system includes: a first core that writes first data by execution of a first program, wherein the first core gives write completion notice after completion of the writing; a second core that refers to the written first data by execution of a second program; and a scheduler that instructs the second core to start the execution of the second program before the execution of the first program is completed when the scheduler is given the write completion notice from the first core by the execution of the first program.

摘要翻译： 多核系统包括：通过执行第一程序写入第一数据的第一核心，其中第一核心在写入完成之后给出写入完成通知; 第二核心，通过执行第二程序来引用所写入的第一数据; 以及调度器，当通过执行第一程序向调度器给予来自第一核的写入完成通知时，在第一程序的执行完成之前指示第二内核开始执行第二程序。

公开(公告)号：US20130054941A1

公开(公告)日：2013-02-28

申请号：US13589354

申请日：2012-08-20

申请人： Masayuki TSUJI

发明人： Masayuki TSUJI

IPC分类号： G06F9/30

CPC分类号： G06F9/30196 ,  G06F9/30 ,  G06F9/30003 ,  G06F9/30181 ,  G06F9/3822 ,  G06F9/3861

摘要： A processor includes: an arithmetic unit configured to execute instructions; an instruction decode part configured to decode the instructions executed in the arithmetic unit and to output opcodes; and an interrupt register configured to receive interrupt signals, wherein the instruction decode part includes an instruction code map that stores the opcodes in correspondence to instructions and outputs the opcodes in accordance with the instructions inputted, and the instruction code map stores a plurality of sets of opcodes to be output as switch opcodes corresponding to additional instructions, the additional instructions are a part of the instructions, and switches the sets of the switch opcodes in accordance with the interrupt signal.

摘要翻译： 处理器包括：被配置为执行指令的算术单元; 指令解码部分，被配置为对在所述算术单元中执行的指令进行解码并输出操作码; 以及中断寄存器，被配置为接收中断信号，其中指令解码部分包括指令代码映射，该指令代码映射根据指令存储操作码，并根据输入的指令输出操作码，并且指令代码映射存储多个 操作码作为对应于附加指令的开关操作码输出，附加指令是指令的一部分，并根据中断信号切换开关操作码组。

公开(公告)号：US20120110307A1

公开(公告)日：2012-05-03

申请号：US13209843

申请日：2011-08-15

申请人： Masayuki TSUJI

发明人： Masayuki TSUJI

IPC分类号： G06F9/30

CPC分类号： G06F9/30178 ,  G06F9/30156

摘要： A compressed instruction processing device has: a compressed instruction expanding circuit which expands a compressed instruction code that include a difference code between an instruction code being a compression object and a reference instruction code and which outputs an expanded instruction code; an instruction buffer storing the instruction code expanded by the compressed instruction expanding circuit; and an execution section executing the instruction code expanded by the compressed instruction expanding circuit, wherein the compressed instruction expanding circuit outputs the expanded instruction code by inputting the instruction code in the instruction buffer as the reference instruction code and adding the reference instruction code and the difference code in the compressed instruction code.

摘要翻译： 压缩指令处理装置具有：压缩指令扩展电路，其扩展包括作为压缩对象的指令代码和参考指令代码之间的差分代码并且输出扩展指令代码的压缩指令代码; 存储由压缩指令扩展电路扩展的指令代码的指令缓冲器; 以及执行由压缩指令扩展电路扩展的指令代码的执行部分，其中压缩指令扩展电路通过将指令缓冲器中的指令代码输入作为参考指令代码并将参考指令代码和差值 压缩指令代码中的代码。

公开(公告)号：US20090172296A1

公开(公告)日：2009-07-02

申请号：US12343251

申请日：2008-12-23

申请人： Masayuki TSUJI ,  Yoshimasa Takebe ,  Akira Nodomi

发明人： Masayuki TSUJI ,  Yoshimasa Takebe ,  Akira Nodomi

IPC分类号： G06F12/08

CPC分类号： G06F12/0802 ,  G06F2212/1044

摘要： A cache memory system including a processing unit and a cache memory which is connected to the processing unit, wherein when a store instruction of storing write data into a certain address is executed, the cache memory system executes selectively one of, a first operation mode of allocating an area of the address to the cache memory in response to a generation of a cache miss due to an access to the address, copying data of the address of the main memory unit to the cache memory and then rewriting the copied data on the cache memory using the write data, and a second operation mode in response to a generation of a cache miss due to the access to the address and storing the write data to the cache memory without copying data of the address of the main memory unit to the allocated area on the cache memory.

摘要翻译： 一种高速缓冲存储器系统，包括连接到处理单元的处理单元和高速缓存存储器，其中当执行将写入数据存储到特定地址的存储指令时，高速缓冲存储器系统选择性地执行以下操作中的一种：第一操作模式 响应于由于访问地址而产生高速缓存未命中而将地址的区域分配给高速缓冲存储器，将主存储器单元的地址的数据复制到高速缓冲存储器，然后在缓存上重写复制的数据 存储器，以及响应于由于访问地址而产生高速缓存未命中的第二操作模式，并且将写入数据存储到高速缓冲存储器，而不将主存储器单元的地址的数据复制到所分配的 缓存中的区域。