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27 条记录 (耗时 0.023 秒)

    Core clock correction in a 2/N mode clocking scheme
    1.
    发明授权
    Core clock correction in a 2/N mode clocking scheme 失效
    核心时钟校正在2 / N模式计时方案

    公开(公告)号：US5834956A

    公开(公告)日：1998-11-10

    申请号：US709379

    申请日：1996-09-06

    申请人： Chakrapani Pathikonda ,  Matthew A. Fisch ,  Javed S. Barkatullah

    发明人： Chakrapani Pathikonda ,  Matthew A. Fisch ,  Javed S. Barkatullah

    IPC分类号： G06F1/12 ,  H03K21/00

    CPC分类号： G06F1/12

    摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

    摘要翻译： 2 / N模式时钟发生器，其通过使用总线时钟使能信号来产生总线时钟信号，从而选择与核心时钟信号同相和异相的总线时钟脉冲。 时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

    Core clock correction in a 2/n mode clocking scheme
    2.
    发明授权
    Core clock correction in a 2/n mode clocking scheme 有权
    2 / n模式计时方案的核心时钟校正

    公开(公告)号：US06268749B1

    公开(公告)日：2001-07-31

    申请号：US09586396

    申请日：2000-05-31

    申请人： Matthew A. Fisch ,  Chakrapani Pathikonda ,  Javed S. Barkatullah

    发明人： Matthew A. Fisch ,  Chakrapani Pathikonda ,  Javed S. Barkatullah

    IPC分类号： H03L700

    CPC分类号： G06F1/12

    摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

    摘要翻译： 2 / N模式时钟发生器，其通过使用总线时钟使能信号来产生总线时钟信号，从而选择与核心时钟信号同相和异相的总线时钟脉冲。 时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

    Core clock correction in a 2/N mode clocking scheme
    3.
    发明授权
    Core clock correction in a 2/N mode clocking scheme 有权
    核心时钟校正在2 / N模式计时方案

    公开(公告)号：US06208180B1

    公开(公告)日：2001-03-27

    申请号：US09170997

    申请日：1998-10-13

    申请人： Matthew A. Fisch ,  Chakrapani Pathikonda ,  Javed S. Barkatullah

    发明人： Matthew A. Fisch ,  Chakrapani Pathikonda ,  Javed S. Barkatullah

    IPC分类号： H03L700

    CPC分类号： G06F1/12

    摘要： A 2/N mode dock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

    摘要翻译： 通过使用总线时钟使能信号来选择与核心时钟信号同相和异相的总线时钟脉冲来产生总线时钟信号的2 / N模式发射器。 时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

    Method and apparatus for preventing logic glitches in a 2/n clocking scheme
    4.
    发明授权
    Method and apparatus for preventing logic glitches in a 2/n clocking scheme 失效
    用于在2 / n计时方案中防止逻辑故障的方法和装置

    公开(公告)号：US5826067A

    公开(公告)日：1998-10-20

    申请号：US709262

    申请日：1996-09-06

    申请人： Matthew A. Fisch ,  Chakrapani Pathikonda

    发明人： Matthew A. Fisch ,  Chakrapani Pathikonda

    IPC分类号： G06F1/12 ,  G06F1/04

    CPC分类号： G06F1/12

    摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

    摘要翻译： 2 / N模式时钟发生器，其通过使用总线时钟使能信号来产生总线时钟信号，从而选择与核心时钟信号同相和异相的总线时钟脉冲。 时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

    Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
    10.
    发明授权
    Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
    用于支持对存储器进行读取，写入和无效操作的方法和装置，其保持缓存一致性

    公开(公告)号：US5909699A

    公开(公告)日：1999-06-01

    申请号：US672422

    申请日：1996-06-28

    申请人： Nitin V. Sarangdhar ,  Michael W. Rhodehamel ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

    发明人： Nitin V. Sarangdhar ,  Michael W. Rhodehamel ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

    IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/14

    CPC分类号： G06F12/0831 ,  G06F12/0833 ,  G06F13/1668

    摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

    摘要翻译： 总线上代理发出的内存请求在保持缓存一致性的同时得到满足。 请求代理可以通过将请求放在总线上向另一代理或存储器单元发出请求。 总线上的每个代理都会窥探总线，以确定是否可以通过访问其缓存来满足发出的请求。 可以使用其缓存来满足请求的代理，即窥探代理，向请求代理发出指示这样的信号。 侦听代理将与请求相对应的高速缓存行放置在由请求代理检索到的总线上。 在读取请求的情况下，存储器单元还从总线检索高速缓存线数据，并将高速缓存行存储在主存储器中。 在写请求的情况下，请求代理随着请求传送总线上的写数据。 该写入数据由临时存储数据的存储单元和监听代理二者检索。 随后，窥探代理通过总线传输整个高速缓存行。 存储器单元检索该高速缓存线，将其与先前存储的写数据合并，并将合并的高速缓存行写入存储器。