公开(公告)号：US20060112249A1

公开(公告)日：2006-05-25

申请号：US10995459

申请日：2004-11-22

申请人： Matthew Bomhoff ,  Brian Cagno ,  John Elliott ,  Carl Jones ,  Robert Kubo ,  Gregg Lucas

发明人： Matthew Bomhoff ,  Brian Cagno ,  John Elliott ,  Carl Jones ,  Robert Kubo ,  Gregg Lucas

IPC分类号： G06F13/00 ,  H04J1/16 ,  G06F13/28

CPC分类号： G06F13/4022 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0635 ,  G06F3/0683

摘要： A method is disclosed to set the signaling rate of a switch domain disposed in an information storage and retrieval system. The method establishes a switch domain target operating speed, and determines if that switch domain target operating speed comprises a first signaling rate. If the switch domain target operating speed comprises a first signaling rate, then the method asserts first Device Control Code bits to each of the plurality of data storage devices, and each of the plurality of data storage devices communicates with the switch using that first signaling rate. If the switch domain target operating speed does not comprise the first signaling rate, then the method asserts second Device Control Code bits to each of the plurality of data storage devices, and each of the plurality of data storage devices communicates with the switch using a second signaling rate.

公开(公告)号：US20060104215A1

公开(公告)日：2006-05-18

申请号：US10993768

申请日：2004-11-18

申请人： Matthew Bomhoff ,  Brian Cagno ,  John Elliott ,  Carl Jones ,  Robert Kubo ,  Gregg Lucas ,  Katherine Tyldesley

发明人： Matthew Bomhoff ,  Brian Cagno ,  John Elliott ,  Carl Jones ,  Robert Kubo ,  Gregg Lucas ,  Katherine Tyldesley

IPC分类号： H04L12/56 ,  H04L12/26 ,  H04J3/14 ,  H04J1/16 ,  H04L1/00 ,  H04L12/28

CPC分类号： H04L41/0896

摘要： A method is disclosed to set the speed of a network. The method supplies a network interconnected with a system controller and a plurality of switch domains, where each of those plurality of switch domains comprises one or more information storage devices and a switch domain controller, and sets by each of the plurality of switch domains a signaling rate for that switch domain. The method queries in-band by the system controller each of the plurality of switch domains for that switch domain's signaling rate, and provides in-band by each of the plurality of switch domains the signaling rate for that switch domain. The method provides in-band by the system controller to each of the plurality of switch domains a first speed selection command specifying a first network speed, and resets by each of the plurality of switch domains the signaling rate for that switch domain to the first network speed.

摘要翻译： 公开了一种设置网络速度的方法。 该方法提供与系统控制器和多个交换机域互连的网络，其中这些多个交换机域中的每一个包括一个或多个信息存储设备和交换机域控制器，并且由多个交换机域中的每一个设置信令 该交换机域的速率。 所述方法由所述系统控制器对所述交换机域的信令速率的所述多个交换机域中的每一个进行带内查询，并且通过所述多个交换机域中的每一个提供所述交换机域的信令速率的带内。 该方法由系统控制器向系统控制器提供指定第一网络速度的第一速度选择命令，并且由多个交换机域中的每一个将该交换机域的信令速率复位到第一网络 速度。

公开(公告)号：US20060104206A1

公开(公告)日：2006-05-18

申请号：US10991577

申请日：2004-11-18

申请人： Matthew Bomhoff ,  Brian Cagno ,  John Elliott ,  Robert Kubo ,  Gregg Lucas

发明人： Matthew Bomhoff ,  Brian Cagno ,  John Elliott ,  Robert Kubo ,  Gregg Lucas

IPC分类号： H04L12/26

CPC分类号： H04L43/00

摘要： An apparatus, system, and method are disclosed for detecting a fibre channel miscabling event. The apparatus includes a detect module, a determine module, and an enable module. The detect module detects a fibre channel cable connection configuration, the determine module determines whether the connection configuration is valid according to preset validity requirements, and the enable module enables a valid fibre channel connection. Additionally, services for implementing such an apparatus, system, and method are disclosed. Implementation of the apparatus, system, and method beneficially reduce risk of data corruption, denial of data access, and similar data communication errors associated with miscabling events.

摘要翻译： 公开了用于检测光纤通道混合事件的装置，系统和方法。 该装置包括检测模块，确定模块和使能模块。 检测模块检测光纤通道电缆连接配置，确定模块根据预设的有效性要求确定连接配置是否有效，启用模块启用有效的光纤通道连接。 此外，公开了实现这种装置，系统和方法的服务。 该设备，系统和方法的实现有利地降低数据损坏的风险，拒绝数据访问以及与通信事件相关的类似的数据通信错误。

公开(公告)号：US20060182110A1

公开(公告)日：2006-08-17

申请号：US11061955

申请日：2005-02-17

申请人： Matthew Bomhoff ,  Brian Cagno ,  John Elliott ,  Robert Kubo ,  Gregg Lucas

发明人： Matthew Bomhoff ,  Brian Cagno ,  John Elliott ,  Robert Kubo ,  Gregg Lucas

IPC分类号： H04L12/56 ,  H04L12/28

CPC分类号： H04L61/2038 ,  H04L12/42 ,  H04L29/12254 ,  H04L29/12839 ,  H04L49/3009 ,  H04L49/357 ,  H04L61/6022

摘要： An apparatus, system, and method are disclosed for fibre channel device addressing. The apparatus includes a mapping module, a receiving module, and an assigning module configured to execute the necessary steps of defining an address assignment map to associate a single logical address with a physical device, receive a request for the logical address defined for the physical device by the address assignment map, and consistently assign the logical address defined by the address assignment map to the physical device. Beneficially, the apparatus, system, and method provide for consistent and reliable fibre channel device addressing.

摘要翻译： 公开了用于光纤通道设备寻址的装置，系统和方法。 该装置包括映射模块，接收模块和分配模块，其被配置为执行定义地址分配映射以将单个逻辑地址与物理设备相关联的必要步骤，接收为物理设备定义的逻辑地址的请求 通过地址分配映射，并且将由地址分配映射定义的逻辑地址一致地分配给物理设备。 有利的是，设备，系统和方法提供了一致和可靠的光纤通道设备寻址。

公开(公告)号：US20060106947A1

公开(公告)日：2006-05-18

申请号：US10994123

申请日：2004-11-18

申请人： Michael Benhase ,  Matthew Bomhoff ,  Brian Cagno ,  John Elliott ,  Robert Kubo ,  Gregg Lucas

发明人： Michael Benhase ,  Matthew Bomhoff ,  Brian Cagno ,  John Elliott ,  Robert Kubo ,  Gregg Lucas

IPC分类号： G06F3/00

CPC分类号： G06F3/0658 ,  G06F3/0607 ,  G06F3/0683

摘要： An information storage and retrieval system is disclosed, wherein that information storage and retrieval system comprises a storage controller, comprising one or more host adapter ports, one or more device adapter ports, a processor, and a Fibre Channel switch. The information storage and retrieval system further comprises a Fibre Channel switch controller consisting essentially of a Fibre Channel switch and a processor. The system further comprises a plurality of data storage devices, where each of those data storage devices is interconnected with the storage controller and with the Fibre Channel switch controller.

摘要翻译： 公开了一种信息存储和检索系统，其中信息存储和检索系统包括存储控制器，其包括一个或多个主机适配器端口，一个或多个设备适配器端口，处理器和光纤通道交换机。 信息存储和检索系统还包括基本上由光纤通道交换机和处理器组成的光纤通道交换机控制器。 该系统还包括多个数据存储设备，其中每个数据存储设备与存储控制器和光纤通道交换机控制器互连。

公开(公告)号：US20060106952A1

公开(公告)日：2006-05-18

申请号：US10992579

申请日：2004-11-18

申请人： Matthew Bomhoff ,  Brian Cagno ,  John Elliott ,  Robert Kubo ,  Gregg Lucas

发明人： Matthew Bomhoff ,  Brian Cagno ,  John Elliott ,  Robert Kubo ,  Gregg Lucas

IPC分类号： G06F3/00

CPC分类号： H04L61/1541 ,  H04L29/12113 ,  H04L29/12216 ,  H04L29/12783 ,  H04L61/2007 ,  H04L61/35 ,  H04L67/16

摘要： An apparatus, system, and method are disclosed for integrating an enclosure. An initialization module initializes a second enclosure. A discovery module discovers a connection of the second enclosure to a first enclosure. An address module creates a valid address for the second enclosure. An assignment module assigns the address to the second enclosure. A power control module cycles power to the second enclosure to reinitialize the second enclosure and set the address.

公开(公告)号：US20060112305A1

公开(公告)日：2006-05-25

申请号：US10989656

申请日：2004-11-16

申请人： Brian Cagno ,  John Elliott ,  Carl Jones ,  Robert Kubo ,  Gregg Lucas

发明人： Brian Cagno ,  John Elliott ,  Carl Jones ,  Robert Kubo ,  Gregg Lucas

IPC分类号： G06F11/00

CPC分类号： G06F1/28 ,  G06F11/1441 ,  G06F11/2015

摘要： An apparatus, system, and method are disclosed for limiting failures in redundant signals. A coordination module generates a power status signal for each of a plurality of power modules. An input module receives a source signal. A signal generation module generates a plurality of output signals from the source signal and at least one power status signal. The output signals are not asserted if at least one power supply is operational. If a device of the signal generation module malfunctions, no more than one output signal is erroneously asserted.

摘要翻译： 公开了用于限制冗余信号中的故障的装置，系统和方法。 协调模块为多个功率模块中的每一个生成电力状态信号。 输入模块接收源信号。 信号产生模块从源信号和至少一个电源状态信号产生多个输出信号。 如果至少有一个电源可用，则输出信号不会被断言。 如果信号发生模块的设备发生故障，则不会有一个以上的输出信号被断言。

公开(公告)号：US20060174044A1

公开(公告)日：2006-08-03

申请号：US11045682

申请日：2005-01-28

申请人： Matthew Bomhoff ,  Brian Cagno ,  Robert Kubo ,  Gregg Lucas

发明人： Matthew Bomhoff ,  Brian Cagno ,  Robert Kubo ,  Gregg Lucas

IPC分类号： G06F13/00

CPC分类号： G06F13/4286 ,  Y02D10/14 ,  Y02D10/151

摘要： A multiple-master Inter Integrated Circuit (“I2C) bus system includes a first master device including a first processing device within a first power boundary and a second master device including a second processing device within a second power boundary connected through a single I2C bus to one or more slave devices. The second master device utilizes a software algorithm or hardware component to detect or manage power up of the first power boundary. Additionally, the second master device includes a bus control algorithm that allows it, once initiated, to communicate with the connected slave device, to direct the first power boundary to activate or detect that the first power boundary has powered up, and to release the I2C bus. Once the first processor has initialized, the first master device acquires control of the I2C bus without arbitration or interference with the second master device.

摘要翻译： 多主器件集成电路（“I2C”）总线系统包括第一主器件，其包括第一电源边界内的第一处理器件和第二主器件，其包括通过单个I2C总线连接的第二电源边界内的第二处理器件， 一个或多个从设备，第二主设备利用软件算法或硬件组件来检测或管理第一电源边界的上电，另外，第二主设备包括总线控制算法，一旦启动，允许其与 连接的从设备，用于引导第一个电源边界来激活或检测到第一个电源边界已经通电，并释放I2C总线。一旦第一个处理器初始化，第一个主设备将在不仲裁的情况下获取I2C总线的控制 或干扰第二主设备。

公开(公告)号：US20060101833A1

公开(公告)日：2006-05-18

申请号：US10988370

申请日：2004-11-12

申请人： Gregg Lucas ,  Robert Kubo ,  Brian Cagno ,  Matthew Bomhoff

发明人： Gregg Lucas ,  Robert Kubo ,  Brian Cagno ,  Matthew Bomhoff

IPC分类号： F25B9/00 ,  F25B49/00 ,  G05D23/32 ,  F25B7/00

CPC分类号： H05K7/20209 ,  F25B49/005 ,  G06F1/206 ,  G06F11/20 ,  G06F11/2033

摘要： A data processing unit including a first active cooling device configured to respond to a first control signal and a second active cooling device configured to respond to a second control signal. The control signals may be any type of control signal suitable to control the operation of the first and second active cooling devices. The data processing unit also includes a first control function selectively capable of providing the first control signal and/or the second control signal, and a second control function selectively capable of providing the first control signal and/or the second control signal. Logic associated with the first and second control functions is included to determine which of the control functions will provide which control signal at a specific time. Logic and/or switching or isolation apparatus is also included to prevent both the first and second control functions from attempting to provide one of the control signals simultaneously.

摘要翻译： 一种数据处理单元，包括被配置为响应于第一控制信号的第一主动冷却装置和被配置为响应于第二控制信号的第二主动冷却装置。 控制信号可以是适于控制第一和第二主动冷却装置的操作的任何类型的控制信号。 数据处理单元还包括选择性地能够提供第一控制信号和/或第二控制信号的第一控制功能，以及选择性地能够提供第一控制信号和/或第二控制信号的第二控制功能。 包括与第一和第二控制功能相关联的逻辑以确定哪个控制功能将在特定时间提供哪个控制信号。 还包括逻辑和/或切换或隔离装置以防止第一和第二控制功能同时尝试提供一个控制信号。

公开(公告)号：US20060031601A1

公开(公告)日：2006-02-09

申请号：US10912973

申请日：2004-08-05

申请人： John Elliott ,  Robert Kubo ,  Carl Jones ,  Gregg Lucas

发明人： John Elliott ,  Robert Kubo ,  Carl Jones ,  Gregg Lucas

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： The method forms a plurality of DMA data payloads each comprising a plurality of first sectors, and sends to a sector format conversion device one or more of those DMA data payloads. The method then overlays the (i)th DMA data payload onto part or all of a plurality of second sectors to form the (i)th converted DMA data payload, enqueues that (i)th converted DMA data payload in a data queue, transmits that (i)th converted DMA data payload to a data storage device, and writes the (i)th converted DMA data payload to an information storage medium.

摘要翻译： 该方法形成多个DMA数据有效载荷，每个DMA数据有效载荷包括多个第一扇区，并向扇区格式转换装置发送这些DMA数据有效载荷中的一个或多个。 该方法然后将第（i）个DMA数据有效载荷叠加到多个第二扇区的部分或全部以形成第（i）个转换的DMA数据有效载荷，排队（i）数据队列中的转换的DMA数据有效载荷， （i）将DMA数据有效负载转换为数据存储设备，并将第（i）个转换的DMA数据有效载荷写入信息存储介质。