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    PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION
    1.
    发明申请
    PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
    具有分支机构错误预测的第二个执行单元的处理程序

    公开(公告)号：US20140195790A1

    公开(公告)日：2014-07-10

    申请号：US13994676

    申请日：2011-12-28

    申请人： Matthew C. Merten ,  Avinash Sodani ,  Sean P. Mirkes ,  Vijaykumar B. Kadgi ,  Bambang Sutanto ,  Chia Yin Kevin Lai ,  Morris Marden ,  Alexandre J. Farcy

    发明人： Matthew C. Merten ,  Avinash Sodani ,  Sean P. Mirkes ,  Vijaykumar B. Kadgi ,  Bambang Sutanto ,  Chia Yin Kevin Lai ,  Morris Marden ,  Alexandre J. Farcy

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

    摘要： A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.

    摘要翻译： 次级跳转执行单元（JEU）并入微处理器以与主JEU同时操作，使得能够执行同时分支操作，并可能检测到多个分支错误预测。 当在同一个指令周期中对两个JEU执行分支操作时，辅助JEU的错误预测处理被划分到主JEU的调度流水线中，使得辅助JEU的分支处理在主JEU的分支处理之后发生，而 初级JEU不处理分支。 此外，在从处理器的重新排序缓冲器接收到nuke命令的情况下，进一步延迟用于辅助JEU的分支处理，以适应主JEU上的nuke的处理。 进一步的实施方案支持促进联合联合国次级方案在某些情况下获得主要联合执行机构的错误预测机制。

    PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR
    2.
    发明申请
    PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR 审中-公开
    在多处理器中基于预测的螺纹选择

    公开(公告)号：US20140201505A1

    公开(公告)日：2014-07-17

    申请号：US13997837

    申请日：2012-03-30

    申请人： Matthew C. Merten ,  Tong Li ,  Vijaykumar B. Kadgi ,  Srikanth T. Srinivasan ,  Christine E. Wang

    发明人： Matthew C. Merten ,  Tong Li ,  Vijaykumar B. Kadgi ,  Srikanth T. Srinivasan ,  Christine E. Wang

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  Y02D10/24

    摘要： A processor includes one or more execution units to execute instructions of a plurality of threads and thread control logic coupled to the execution units to predict whether a first of the plurality of threads is ready for selection in a current cycle based on readiness of instructions of the first thread in one or more previous cycles, to predict whether a second of the plurality of threads is ready for selection in the current cycle based on readiness of instructions of the second thread in the one or more previous cycles, and to select one of the first and second threads in the current cycle based on the predictions.

    摘要翻译： 处理器包括一个或多个执行单元，用于执行多个线程的指令和与执行单元耦合的线程控制逻辑，以基于当前周期的指令的准备就绪来预测多个线程中的第一个线程是否准备好在当前周期中进行选择 在一个或多个先前循环中的第一线程，以基于所述一个或多个先前循环中的第二线程的指令的准备来预测多个线程中的第二线程是否准备好在当前周期中进行选择，并且选择 基于预测的当前循环中的第一和第二个线程。

    Systems and methods for flag tracking in move elimination operations
    3.
    发明授权
    Systems and methods for flag tracking in move elimination operations 有权
    移动消除操作中标志跟踪的系统和方法

    公开(公告)号：US09292288B2

    公开(公告)日：2016-03-22

    申请号：US13861009

    申请日：2013-04-11

    申请人： Vijaykumar B. Kadgi ,  Jeremy R. Anderson ,  James D. Hadley ,  Tong Li ,  Matthew C. Merten

    发明人： Vijaykumar B. Kadgi ,  Jeremy R. Anderson ,  James D. Hadley ,  Tong Li ,  Matthew C. Merten

    IPC分类号： G06F9/30 ,  G06F9/45 ,  G06F9/38

    CPC分类号： G06F9/30105 ,  G06F8/443 ,  G06F9/30032 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/30181 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

    摘要： Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.

    摘要翻译： 涉及移动消除的数据处理操作中标志跟踪的系统和方法。 示例性处理系统包括包括多个物理寄存器值的第一数据结构; 第二数据结构，包括引用第一数据结构的元素的多个指针; 包括多个移动消除集合的第三数据结构，每个移动消除集合包括表示两个或多个逻辑数据寄存器的两个或多个位，所述第三数据结构还包括与每个移动消除集相关联的至少一个位，所述至少一个 位表示一个或多个逻辑标志寄存器; 第四数据结构，包括与标志寄存器共享第一数据结构的元素的数据寄存器的标识符; 以及配置为执行移动消除操作的移动消除逻辑。

    Scheduler Implementing Dependency Matrix Having Restricted Entries
    5.
    发明申请
    Scheduler Implementing Dependency Matrix Having Restricted Entries 审中-公开
    调度器实现具有限制条目的依赖矩阵

    公开(公告)号：US20140181476A1

    公开(公告)日：2014-06-26

    申请号：US13723684

    申请日：2012-12-21

    申请人： Srikanth T. Srinivasan ,  Matthew C. Merten ,  Bambang Sutanto ,  Rahul R. Kulkarni ,  Justin M. Deinlein ,  James D. Hadley

    发明人： Srikanth T. Srinivasan ,  Matthew C. Merten ,  Bambang Sutanto ,  Rahul R. Kulkarni ,  Justin M. Deinlein ,  James D. Hadley

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3838

    摘要： A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.

    摘要翻译： 公开了实现具有限制条目的依赖矩阵的调度器。 本公开的处理装置包括：解码单元，用于对指令进行解码;以及可通信地耦合到解码单元的调度器。 在一个实施例中，调度器被配置为接收解码的指令，确定解码的指令限定为由调度器维护的依赖矩阵中的受限保留站（RS）条目类型的分配，识别依赖矩阵中的RS条目 将所识别的空闲RS条目中的一个分配给依赖矩阵中的解码指令的信息，并且通过解码指令的源依赖性信息更新与所要求的RS条目相对应的依赖矩阵的一行。

    ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION
    7.
    发明申请
    ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
    启用和禁用分支机构错误预测的第二个执行单位

    公开(公告)号：US20140156977A1

    公开(公告)日：2014-06-05

    申请号：US13994699

    申请日：2011-12-28

    申请人： Mark J. Dechene ,  Matthew C. Merten ,  Sean P. Mirkes

    发明人： Mark J. Dechene ,  Matthew C. Merten ,  Sean P. Mirkes

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3861 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3885

    摘要： Techniques are described for enabling and/or disabling a secondary jump execution unit (JEU) in a micro-processor. The secondary JEU is incorporated in the micro-processor to operate concurrently with a primary JEU, and to enable the handling of simultaneous branch mispredicts on multiple branches. Activation and deactivation of the secondary JEU may be controlled by a pressure counter or a confidence counter. A pressure counter mechanism increments a count for each branch operation executed within the processor and decrements the count by a decay value during each cycle. A confidence counter mechanism increments a count for each correctly predicted branch, and decrements the count for each mispredict. Each counter signals an activation component, such as a port binding hardware component, to begin binding micro-operations to the secondary JEU when the counter exceeds an activation threshold. The counter mechanism may be thread-agnostic or thread-specific.

    摘要翻译： 描述了在微处理器中启用和/或禁用辅助跳转执行单元（JEU）的技术。 次级JEU被并入微处理器以与主JEU同时操作，并且能够在多个分支上处理同时的分支错误预测。 次级JEU的激活和停用可以由压力计数器或置信计数器来控制。 压力计数器机构增加在处理器内执行的每个分支操作的计数，并在每个周期期间将计数减去衰减值。 置信度计数机制增加每个正确预测分支的计数，并减少每个错误预测的计数。 当计数器超过激活阈值时，每个计数器发出一个激活组件，例如端口绑定硬件组件，开始将微操作绑定到辅助JEU。 计数器机制可能是线程不可知或线程特定的。

    ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION
    9.
    发明申请
    ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION 有权
    增强环路检测器驱动逻辑优化

    公开(公告)号：US20140189306A1

    公开(公告)日：2014-07-03

    申请号：US13728273

    申请日：2012-12-27

    申请人： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

    发明人： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30065 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3885

    摘要： An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.

    摘要翻译： 在处理器中提供增强的循环流检测机制以降低功耗。 处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。 处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。 该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。

    Enhanced loop streaming detector to drive logic optimization
    10.
    发明授权
    Enhanced loop streaming detector to drive logic optimization 有权
    增强循环流检测器驱动逻辑优化

    公开(公告)号：US09354875B2

    公开(公告)日：2016-05-31

    申请号：US13728273

    申请日：2012-12-27

    申请人： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

    发明人： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30065 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3885

    摘要： An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.

    摘要翻译： 在处理器中提供增强的循环流检测机制以降低功耗。 处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。 处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。 该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。