PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION
    1.
    发明申请
    PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
    具有分支机构错误预测的第二个执行单元的处理程序

    公开(公告)号:US20140195790A1

    公开(公告)日:2014-07-10

    申请号:US13994676

    申请日:2011-12-28

    IPC分类号: G06F9/38

    摘要: A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.

    摘要翻译: 次级跳转执行单元(JEU)并入微处理器以与主JEU同时操作,使得能够执行同时分支操作,并可能检测到多个分支错误预测。 当在同一个指令周期中对两个JEU执行分支操作时,辅助JEU的错误预测处理被划分到主JEU的调度流水线中,使得辅助JEU的分支处理在主JEU的分支处理之后发生,而 初级JEU不处理分支。 此外,在从处理器的重新排序缓冲器接收到nuke命令的情况下,进一步延迟用于辅助JEU的分支处理,以适应主JEU上的nuke的处理。 进一步的实施方案支持促进联合联合国次级方案在某些情况下获得主要联合执行机构的错误预测机制。

    ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION
    8.
    发明申请
    ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
    启用和禁用分支机构错误预测的第二个执行单位

    公开(公告)号:US20140156977A1

    公开(公告)日:2014-06-05

    申请号:US13994699

    申请日:2011-12-28

    IPC分类号: G06F9/38

    摘要: Techniques are described for enabling and/or disabling a secondary jump execution unit (JEU) in a micro-processor. The secondary JEU is incorporated in the micro-processor to operate concurrently with a primary JEU, and to enable the handling of simultaneous branch mispredicts on multiple branches. Activation and deactivation of the secondary JEU may be controlled by a pressure counter or a confidence counter. A pressure counter mechanism increments a count for each branch operation executed within the processor and decrements the count by a decay value during each cycle. A confidence counter mechanism increments a count for each correctly predicted branch, and decrements the count for each mispredict. Each counter signals an activation component, such as a port binding hardware component, to begin binding micro-operations to the secondary JEU when the counter exceeds an activation threshold. The counter mechanism may be thread-agnostic or thread-specific.

    摘要翻译: 描述了在微处理器中启用和/或禁用辅助跳转执行单元(JEU)的技术。 次级JEU被并入微处理器以与主JEU同时操作,并且能够在多个分支上处理同时的分支错误预测。 次级JEU的激活和停用可以由压力计数器或置信计数器来控制。 压力计数器机构增加在处理器内执行的每个分支操作的计数,并在每个周期期间将计数减去衰减值。 置信度计数机制增加每个正确预测分支的计数,并减少每个错误预测的计数。 当计数器超过激活阈值时,每个计数器发出一个激活组件,例如端口绑定硬件组件,开始将微操作绑定到辅助JEU。 计数器机制可能是线程不可知或线程特定的。