公开(公告)号：US20150378412A1

公开(公告)日：2015-12-31

申请号：US14318999

申请日：2014-06-30

Applicant: Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson

Inventor： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson

IPC: G06F1/28 ,  G06F1/26 ,  G06F12/08 ,  G06F1/32

CPC classification number: G06F1/3206 ,  G06F9/3824 ,  G06F9/3836

Abstract: In an embodiment, a processor includes at least one core including a first core. The first core includes memory execution logic to execute one or more memory instructions, memory dispatch logic to output a plurality of memory instructions to the memory execution logic, and reactive memory instruction tracking logic. The reactive memory instruction tracking logic is to detect an onset of a memory instruction high power event associated with execution of at least one of the memory instructions, and to indicate to the memory dispatch logic to throttle output of the memory instructions to the memory execution logic responsive to detection of the onset of the memory instruction high power event. The processor also includes cache memory coupled to the at least one core. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括至少一个包括第一核心的核心。 第一核心包括执行一个或多个存储器指令的存储器执行逻辑，将存储器指令输出到存储器执行逻辑的存储器调度逻辑以及无效存储器指令跟踪逻辑。 反应性存储器指令跟踪逻辑是检测与执行至少一个存储器指令相关联的存储器指令高功率事件的开始，并且向存储器调度逻辑指示将存储器指令的输出调节到存储器执行逻辑 响应于检测到存储器指令高功率事件的发生。 处理器还包括耦合到至少一个核的高速缓存存储器。 描述和要求保护其他实施例。

公开(公告)号：US09134788B2

公开(公告)日：2015-09-15

申请号：US13340511

申请日：2011-12-29

Applicant: Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

Inventor： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  Y02D10/152

Abstract: Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.

Abstract translation: 一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示 作为执行第二组操作的结果的处理器。 当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。

公开(公告)号：US20150178077A1

公开(公告)日：2015-06-25

申请号：US14139263

申请日：2013-12-23

Applicant: SRIKANTH T. SRINIVASAN ,  MARK J. DECHENE ,  YURY N. ILIN ,  JUSTIN M. DEINLEIN ,  CHRISTINE E. WANG ,  MATTHEW C. MERTEN

Inventor： SRIKANTH T. SRINIVASAN ,  MARK J. DECHENE ,  YURY N. ILIN ,  JUSTIN M. DEINLEIN ,  CHRISTINE E. WANG ,  MATTHEW C. MERTEN

IPC: G06F9/30

CPC classification number: G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3885

Abstract: A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.

Abstract translation: 处理器包括执行第一指令和第二指令的逻辑。 第一条指令在第二条指令之前被排序。 每个指令引用分配给相应物理寄存器的相应逻辑寄存器。 该处理器还包括在退出第一指令之前将第二指令的物理寄存器重新分配给另一个逻辑寄存器的逻辑。

公开(公告)号：US20140189306A1

公开(公告)日：2014-07-03

申请号：US13728273

申请日：2012-12-27

Applicant: Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

Inventor： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

IPC: G06F9/30

CPC classification number: G06F9/30065 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3885

Abstract: An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.

Abstract translation: 在处理器中提供增强的循环流检测机制以降低功耗。 处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。 处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。 该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。

公开(公告)号：US20140025901A1

公开(公告)日：2014-01-23

申请号：US14033463

申请日：2013-09-21

Applicant: Quinn A. Jacobson ,  Anne C. Bracy ,  Hong Wang ,  John P. Shen ,  Per Hammarlund ,  Matthew C. Merten ,  Suresh Srinivas ,  Kshitij A. Doshi ,  Gautham Chinya ,  Bratin Saha ,  Ali-Reza Adi-Tabatabai ,  Gad Sheaffer

Inventor： Quinn A. Jacobson ,  Anne C. Bracy ,  Hong Wang ,  John P. Shen ,  Per Hammarlund ,  Matthew C. Merten ,  Suresh Srinivas ,  Kshitij A. Doshi ,  Gautham Chinya ,  Bratin Saha ,  Ali-Reza Adi-Tabatabai ,  Gad Sheaffer

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F11/3471 ,  G06F11/3648 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/145 ,  G06F2201/865

Abstract: A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.

Abstract translation: 使用存储器属性将信息中继到程序或其他代理的技术。 更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

公开(公告)号：US20130205119A1

公开(公告)日：2013-08-08

申请号：US13538951

申请日：2012-06-29

Applicant: Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F9/46

CPC classification number: G06F11/28 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/466 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/2236 ,  G06F11/25 ,  G06F11/263 ,  G06F12/0811 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/20 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/608 ,  G06F2212/621 ,  G11C7/1072

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Abstract translation: 公开了新的指令，逻辑，方法和装置来测试事务执行状态。 实施例包括解码第一指令以启动事务区域。 响应于第一指令，生成一组架构状态寄存器的检查点，并跟踪与第一指令相关联的事务区域中的处理元件的存储器访问。 然后解码用于检测事务区域的事务执行的第二指令。 执行对第二指令的解码的操作，以确定第二指令的执行上下文是否在事务区域内。 然后响应于第二指令，更新第一标志。 在一些实施例中，可以可选地更新寄存器和/或响应于第二指令任选地更新第二标志。

公开(公告)号：US07516313B2

公开(公告)日：2009-04-07

申请号：US11027392

申请日：2004-12-29

Applicant: Bratin Saha ,  Matthew C. Merten ,  Sebastien Hily ,  David A. Koufaty ,  Per Hammarlund

Inventor： Bratin Saha ,  Matthew C. Merten ,  Sebastien Hily ,  David A. Koufaty ,  Per Hammarlund

IPC: G06F13/376 ,  G06F9/38 ,  G06F13/18

CPC classification number: G06F9/3851 ,  G06F9/526

Abstract: In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括用于预测在程序中要执行的操作的竞争的预测器。 可以基于预测的结果来处理该操作，该结果可以基于多个独立的预测。 在一个实施例中，如果没有预测到争用，则可以优化操作。 描述和要求保护其他实施例。

公开(公告)号：US09268596B2

公开(公告)日：2016-02-23

申请号：US13538951

申请日：2012-06-29

Applicant: Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F11/28 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/466 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/2236 ,  G06F11/25 ,  G06F11/263 ,  G06F12/0811 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/20 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/608 ,  G06F2212/621 ,  G11C7/1072

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Abstract translation: 公开了新的指令，逻辑，方法和装置来测试事务执行状态。 实施例包括解码第一指令以启动事务区域。 响应于第一指令，生成一组架构状态寄存器的检查点，并跟踪与第一指令相关联的事务区域中的处理元件的存储器访问。 然后解码用于检测事务区域的事务执行的第二指令。 执行对第二指令的解码的操作，以确定第二指令的执行上下文是否在事务区域内。 然后响应于第二指令，更新第一标志。 在一些实施例中，可以可选地更新寄存器和/或响应于第二指令任选地更新第二标志。

公开(公告)号：US20150346804A1

公开(公告)日：2015-12-03

申请号：US14823994

申请日：2015-08-11

Applicant: Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

Inventor： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  Y02D10/152

Abstract: Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.

Abstract translation: 一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示 作为执行第二组操作的结果的处理器。 当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。

公开(公告)号：US20150007188A1

公开(公告)日：2015-01-01

申请号：US13931864

申请日：2013-06-29

Applicant: Bambang SUTANTO ,  Srikanth T. SRINIVASAN ,  Matthew C. MERTEN ,  Chia Yin Kevin LAI ,  Ammon J CHRISTIANSEN ,  Justin M DEINLEIN

Inventor： Bambang SUTANTO ,  Srikanth T. SRINIVASAN ,  Matthew C. MERTEN ,  Chia Yin Kevin LAI ,  Ammon J CHRISTIANSEN ,  Justin M DEINLEIN

IPC: G06F9/50

CPC classification number: G06F9/384 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/4881

Abstract: A processor and method are described for scheduling operations for execution within a reservation station. For example, a method in accordance with one embodiment of the invention includes the operations of: classifying a plurality of operations based on the execution ports usable to execute those operations; allocating the plurality of operations into groups within a reservation station based on the classification, wherein each group is serviced by one or more execution ports corresponding to the classification, and wherein two or more entries within a group share a common read port and a common write port; dynamically scheduling two or more operations in a group for concurrent execution based on the ports capable of executing those operations and a relative age of the operations.

Abstract translation: 描述了用于在保留站内执行的调度操作的处理器和方法。 例如，根据本发明的一个实施例的方法包括以下操作：基于可用于执行这些操作的执行端口对多个操作进行分类; 基于分类，将多个操作分配到保留站内的组中，其中每个组由对应于分类的一个或多个执行端口服务，并且其中组内的两个或多个条目共享公共读取端口和公共写入 港口; 基于能够执行这些操作的端口和操作的相对年龄，动态地调度用于并发执行的组中的两个或更多个操作。