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    ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION
    1.
    发明申请
    ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
    启用和禁用分支机构错误预测的第二个执行单位

    公开(公告)号：US20140156977A1

    公开(公告)日：2014-06-05

    申请号：US13994699

    申请日：2011-12-28

    申请人： Mark J. Dechene ,  Matthew C. Merten ,  Sean P. Mirkes

    发明人： Mark J. Dechene ,  Matthew C. Merten ,  Sean P. Mirkes

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3861 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3885

    摘要： Techniques are described for enabling and/or disabling a secondary jump execution unit (JEU) in a micro-processor. The secondary JEU is incorporated in the micro-processor to operate concurrently with a primary JEU, and to enable the handling of simultaneous branch mispredicts on multiple branches. Activation and deactivation of the secondary JEU may be controlled by a pressure counter or a confidence counter. A pressure counter mechanism increments a count for each branch operation executed within the processor and decrements the count by a decay value during each cycle. A confidence counter mechanism increments a count for each correctly predicted branch, and decrements the count for each mispredict. Each counter signals an activation component, such as a port binding hardware component, to begin binding micro-operations to the secondary JEU when the counter exceeds an activation threshold. The counter mechanism may be thread-agnostic or thread-specific.

    摘要翻译： 描述了在微处理器中启用和/或禁用辅助跳转执行单元（JEU）的技术。 次级JEU被并入微处理器以与主JEU同时操作，并且能够在多个分支上处理同时的分支错误预测。 次级JEU的激活和停用可以由压力计数器或置信计数器来控制。 压力计数器机构增加在处理器内执行的每个分支操作的计数，并在每个周期期间将计数减去衰减值。 置信度计数机制增加每个正确预测分支的计数，并减少每个错误预测的计数。 当计数器超过激活阈值时，每个计数器发出一个激活组件，例如端口绑定硬件组件，开始将微操作绑定到辅助JEU。 计数器机制可能是线程不可知或线程特定的。

    PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION
    3.
    发明申请
    PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
    具有分支机构错误预测的第二个执行单元的处理程序

    公开(公告)号：US20140195790A1

    公开(公告)日：2014-07-10

    申请号：US13994676

    申请日：2011-12-28

    申请人： Matthew C. Merten ,  Avinash Sodani ,  Sean P. Mirkes ,  Vijaykumar B. Kadgi ,  Bambang Sutanto ,  Chia Yin Kevin Lai ,  Morris Marden ,  Alexandre J. Farcy

    发明人： Matthew C. Merten ,  Avinash Sodani ,  Sean P. Mirkes ,  Vijaykumar B. Kadgi ,  Bambang Sutanto ,  Chia Yin Kevin Lai ,  Morris Marden ,  Alexandre J. Farcy

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

    摘要： A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.

    摘要翻译： 次级跳转执行单元（JEU）并入微处理器以与主JEU同时操作，使得能够执行同时分支操作，并可能检测到多个分支错误预测。 当在同一个指令周期中对两个JEU执行分支操作时，辅助JEU的错误预测处理被划分到主JEU的调度流水线中，使得辅助JEU的分支处理在主JEU的分支处理之后发生，而 初级JEU不处理分支。 此外，在从处理器的重新排序缓冲器接收到nuke命令的情况下，进一步延迟用于辅助JEU的分支处理，以适应主JEU上的nuke的处理。 进一步的实施方案支持促进联合联合国次级方案在某些情况下获得主要联合执行机构的错误预测机制。

    Method And Apparatus To Prevent Voltage Droop In A Computer
    6.
    发明申请
    Method And Apparatus To Prevent Voltage Droop In A Computer 有权
    防止电脑电压下降的方法和装置

    公开(公告)号：US20150378412A1

    公开(公告)日：2015-12-31

    申请号：US14318999

    申请日：2014-06-30

    申请人： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson

    发明人： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson

    IPC分类号： G06F1/28 ,  G06F1/26 ,  G06F12/08 ,  G06F1/32

    CPC分类号： G06F1/3206 ,  G06F9/3824 ,  G06F9/3836

    摘要： In an embodiment, a processor includes at least one core including a first core. The first core includes memory execution logic to execute one or more memory instructions, memory dispatch logic to output a plurality of memory instructions to the memory execution logic, and reactive memory instruction tracking logic. The reactive memory instruction tracking logic is to detect an onset of a memory instruction high power event associated with execution of at least one of the memory instructions, and to indicate to the memory dispatch logic to throttle output of the memory instructions to the memory execution logic responsive to detection of the onset of the memory instruction high power event. The processor also includes cache memory coupled to the at least one core. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括至少一个包括第一核心的核心。 第一核心包括执行一个或多个存储器指令的存储器执行逻辑，将存储器指令输出到存储器执行逻辑的存储器调度逻辑以及无效存储器指令跟踪逻辑。 反应性存储器指令跟踪逻辑是检测与执行至少一个存储器指令相关联的存储器指令高功率事件的开始，并且向存储器调度逻辑指示将存储器指令的输出调节到存储器执行逻辑 响应于检测到存储器指令高功率事件的发生。 处理器还包括耦合到至少一个核的高速缓存存储器。 描述和要求保护其他实施例。

    Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuit
    7.
    发明授权
    Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuit 有权
    能量效率和节能的方法，装置和系统，包括检测和控制处理电路中的电流斜坡

    公开(公告)号：US09134788B2

    公开(公告)日：2015-09-15

    申请号：US13340511

    申请日：2011-12-29

    申请人： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

    发明人： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3243 ,  Y02D10/152

    摘要： Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.

    摘要翻译： 一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示 作为执行第二组操作的结果的处理器。 当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。

    ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION
    8.
    发明申请
    ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION 有权
    增强环路检测器驱动逻辑优化

    公开(公告)号：US20140189306A1

    公开(公告)日：2014-07-03

    申请号：US13728273

    申请日：2012-12-27

    申请人： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

    发明人： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30065 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3885

    摘要： An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.

    摘要翻译： 在处理器中提供增强的循环流检测机制以降低功耗。 处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。 处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。 该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。