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公开(公告)号：US09239798B2
公开(公告)日：2016-01-19
申请号：US13233028
申请日：2011-09-15
CPC分类号： G06F12/0897 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F12/0811 , G06F12/0862 , G06F12/0886 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
摘要： A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource.
摘要翻译： 预取消除仲裁器通过任意取消推测性预取来改善对共享存储器资源的访问。 预取消除仲裁器将一组任意策略应用于推测预取以选择一个或多个接收到的推测性预取以取消。 所选择的推测预取被取消，并且每个取消的推测预取的取消通知被发送到诸如与取消的推测预取相关联的处理器本地的预取单元或本地存储器仲裁器的更高级存储器组件。 该组任意策略用于减少对共享内存资源的内存访问。
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公开(公告)号：US20120072702A1
公开(公告)日：2012-03-22
申请号：US13233028
申请日：2011-09-15
IPC分类号： G06F9/312
CPC分类号： G06F12/0897 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F12/0811 , G06F12/0862 , G06F12/0886 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
摘要： A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource.
摘要翻译： 预取消除仲裁器通过任意取消推测性预取来改善对共享存储器资源的访问。 预取消除仲裁器将一组任意策略应用于推测预取以选择一个或多个接收到的推测性预取以取消。 所选择的推测预取被取消，并且每个取消的推测预取的取消通知被发送到诸如与取消的推测预取相关联的处理器本地的预取单元或本地存储器仲裁器的更高级存储器组件。 该组任意策略用于减少对共享内存资源的内存访问。
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公开(公告)号：US08806110B2
公开(公告)日：2014-08-12
申请号：US13239063
申请日：2011-09-21
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
摘要： A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the requestor originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission. The segment registers translate the logical address from the requestor to a physical address within a larger address space.
摘要翻译： 一种管理来自多个请求者的存储器访问请求的存储器管理和保护系统。 基于每个存储器访问请求附带的权限标识符，基于请求者的权限级别允许或不允许内存访问。 扩展存储器控制器基于特权标识符选择适当的段寄存器集合，以确保将请求与发起请求的请求者相关联的段寄存器进行比较和转换。 一组映射寄存器允许将每个权限标识符灵活映射到适当的访问权限。 段寄存器将逻辑地址从请求者转换为更大地址空间内的物理地址。
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公开(公告)号：US20120191899A1
公开(公告)日：2012-07-26
申请号：US13239063
申请日：2011-09-21
IPC分类号： G06F12/14
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
摘要： A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the requestor originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission. The segment registers translate the logical address from the requestor to a physical address within a larger address space.
摘要翻译： 一种管理来自多个请求者的存储器访问请求的存储器管理和保护系统。 基于每个存储器访问请求附带的权限标识符，基于请求者的权限级别允许或不允许内存访问。 扩展存储器控制器基于特权标识符选择适当的段寄存器集合，以确保将请求与发起请求的请求者相关联的段寄存器进行比较和转换。 一组映射寄存器允许将每个权限标识符灵活映射到适当的访问权限。 段寄存器将逻辑地址从请求者转换为更大地址空间内的物理地址。
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公开(公告)号：US20120072796A1
公开(公告)日：2012-03-22
申请号：US13237917
申请日：2011-09-20
申请人： Kai Chirca , Timothy D. Anderson , Amitabh Menon
发明人： Kai Chirca , Timothy D. Anderson , Amitabh Menon
CPC分类号： G06F12/0897 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F12/0811 , G06F12/0862 , G06F12/0886 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
摘要： A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.
摘要翻译： 存储器验证管理器保留一段时间来独占访问具有存储线的存储器，其中验证码为每个存储器线提供一定程度的错误检测和校正。 存储器验证管理器基于每个存储器线遇到的有效性的指示来读取，处理和校正每个存储器行的至少一些内容。 新数据是响应验证码而编写的。 同样，当有效字段指示还没有为存储器行写入验证码时，可以更新每一行的有效字段和为存储器编写的新验证码。 存储器验证管理器处理从第一存储器线读取的数据，同时读取或写入另一存储器线以最小化擦除存储器线的过程的延迟。
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公开(公告)号：US08732551B2
公开(公告)日：2014-05-20
申请号：US13237917
申请日：2011-09-20
申请人： Kai Chirca , Timothy D. Anderson , Amitabh Menon
发明人： Kai Chirca , Timothy D. Anderson , Amitabh Menon
IPC分类号： G11C29/00
CPC分类号： G06F12/0897 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F12/0811 , G06F12/0862 , G06F12/0886 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
摘要： A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.
摘要翻译： 存储器验证管理器保留一段时间来独占访问具有存储线的存储器，其中验证码为每个存储器线提供一定程度的错误检测和校正。 存储器验证管理器基于每个存储器线遇到的有效性的指示来读取，处理和校正每个存储器行的至少一些内容。 新数据是响应验证码而编写的。 同样，当有效字段指示还没有为存储器行写入验证码时，可以更新每一行的有效字段和为存储器编写的新验证码。 存储器验证管理器处理从第一存储器线读取的数据，同时读取或写入另一存储器线以最小化擦除存储器线的过程的延迟。
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公开(公告)号：US08732370B2
公开(公告)日：2014-05-20
申请号：US13212384
申请日：2011-08-18
申请人： Kai Chirca , Timothy D Anderson , Amitabh Menon
发明人： Kai Chirca , Timothy D Anderson , Amitabh Menon
IPC分类号： G06F13/14
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
摘要： An arbiter is provided for arbitrating for access to a shared resource by a plurality of requesters and by a background requester in a processing system. A priority value is assigned to each of the plurality of requestors. A multilayer arbitration contest is performed to resolve each conflict in transaction requests to the shared resource, however, a requester of the plurality of requesters having a highest priority value does not always win an arbitration contest. An arbitration contest will be overridden whenever the background requester initiates a transaction request, such that the background requester always wins the overridden arbitration contest. The shared resource is accessed by the winner of each arbitration contest.
摘要翻译： 提供仲裁器用于仲裁由多个请求者和处理系统中的后台请求者访问共享资源。 优先级值被分配给多个请求者中的每一个。 执行多层仲裁比赛以解决对共享资源的交易请求中的每个冲突，然而，具有最高优先级值的多个请求者的请求者并不总是赢得仲裁比赛。 当后台请求者启动交易请求时，仲裁比赛将被覆盖，以便后台请求者总是胜过被覆盖的仲裁比赛。 共享资源由每个仲裁大赛的获胜者访问。
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公开(公告)号：US20120072631A1
公开(公告)日：2012-03-22
申请号：US13212384
申请日：2011-08-18
申请人： Kai Chirca , Timothy D. Anderson , Amitabh Menon
发明人： Kai Chirca , Timothy D. Anderson , Amitabh Menon
IPC分类号： G06F13/366
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
摘要： An arbiter is provided for arbitrating for access to a shared resource by a plurality of requesters and by a background requester in a processing system. A priority value is assigned to each of the plurality of requestors. A multilayer arbitration contest is performed to resolve each conflict in transaction requests to the shared resource, however, a requester of the plurality of requesters having a highest priority value does not always win an arbitration contest. An arbitration contest will be overridden whenever the background requester initiates a transaction request, such that the background requester always wins the overridden arbitration contest. The shared resource is accessed by the winner of each arbitration contest.
摘要翻译： 提供仲裁器用于仲裁由多个请求者和处理系统中的后台请求者访问共享资源。 优先级值被分配给多个请求者中的每一个。 执行多层仲裁比赛以解决对共享资源的交易请求中的每个冲突，然而，具有最高优先级值的多个请求者的请求者并不总是赢得仲裁比赛。 当后台请求者启动交易请求时，仲裁比赛将被覆盖，以便后台请求者总是胜过被覆盖的仲裁比赛。 共享资源由每个仲裁大赛的获胜者访问。
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9.发明授权公开(公告)号：US08683114B2
公开(公告)日：2014-03-25
申请号：US13238989
申请日：2011-09-21
IPC分类号： G06F13/00
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
摘要： A memory management and protection system that incorporates device security features that support a distributed, shared memory system. The concept of secure regions of memory and secure code execution is supported, and a mechanism is provided to extend a chain of trust from a known, fixed secure boot ROM to the actual secure code execution. Furthermore, the system keeps a secure address threshold that is only programmable by a secure supervisor, and will only allow secure access requests that are above this threshold.
摘要翻译： 内存管理和保护系统，其中集成了支持分布式共享内存系统的设备安全功能。 支持存储器和安全代码执行的安全区域的概念，并且提供了一种机制来将信任链从已知的固定安全引导ROM扩展到实际的安全代码执行。 此外，系统保持仅由安全监督程序编程的安全地址阈值，并且将仅允许高于该阈值的安全访问请求。
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10.发明授权公开(公告)号：US09110845B2
公开(公告)日：2015-08-18
申请号：US13195555
申请日：2011-08-01
IPC分类号： G06F12/14 , G06F13/366 , G06F21/78 , G06F21/79
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
摘要： A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request.
摘要翻译： 一种管理来自多个请求者的存储器访问请求的存储器管理和保护系统。 基于主机的权限级别（通常是根据伴随每个存储器访问请求的权限标识符发起请求的CPU）允许或不允许内存访问。 诸如DMA控制器的副主人继承了始发主机的权限标识符。 扩展存储器控制器基于特权标识符选择适当的段寄存器集合，以确保请求被与发起请求的主机相关联的段寄存器进行比较和转换。
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