利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

170 条记录 (耗时 0.038 秒)

    Flat lower bottom electrode for phase change memory cell
    1.
    发明授权
    Flat lower bottom electrode for phase change memory cell 失效
    用于相变存储单元的平底下电极

    公开(公告)号：US08471236B2

    公开(公告)日：2013-06-25

    申请号：US13550091

    申请日：2012-07-16

    申请人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Alejandro G. Schrott

    发明人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Alejandro G. Schrott

    IPC分类号： H01L29/40

    CPC分类号： H01L45/148 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.

    摘要翻译： 一种具有平底下电极的相变存储单元及其制造方法。 该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面 导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极 。

    Flat lower bottom electrode for phase change memory cell
    2.
    发明授权
    Flat lower bottom electrode for phase change memory cell 有权
    用于相变存储单元的平底下电极

    公开(公告)号：US08283650B2

    公开(公告)日：2012-10-09

    申请号：US12550048

    申请日：2009-08-28

    申请人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Alejandro G. Schrott

    发明人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Alejandro G. Schrott

    IPC分类号： H01L45/00

    CPC分类号： H01L45/148 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.

    摘要翻译： 一种具有平底下电极的相变存储单元及其制造方法。 该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面 导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极 。

    FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL
    4.
    发明申请
    FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL 失效
    平底下电极用于相变记忆体

    公开(公告)号：US20120280197A1

    公开(公告)日：2012-11-08

    申请号：US13550091

    申请日：2012-07-16

    申请人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Alejandro G. Schrott

    发明人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Alejandro G. Schrott

    IPC分类号： H01L45/00

    CPC分类号： H01L45/148 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.

    摘要翻译： 一种具有平底下电极的相变存储单元及其制造方法。 该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面 导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极 。

    UNIFORM CRITICAL DIMENSION SIZE PORE FOR PCRAM APPLICATION
    6.
    发明申请
    UNIFORM CRITICAL DIMENSION SIZE PORE FOR PCRAM APPLICATION 审中-公开
    用于PCRAM应用的均匀尺寸尺寸孔

    公开(公告)号：US20080164453A1

    公开(公告)日：2008-07-10

    申请号：US11620671

    申请日：2007-01-07

    申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Eirc A. Joseph ,  Alejandro G. Schrott

    发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Eirc A. Joseph ,  Alejandro G. Schrott

    IPC分类号： H01L47/00 ,  H01L21/28

    CPC分类号： H01L45/1683 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

    摘要： A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material.

    摘要翻译： 存储单元及其制造方法，其包括沉积在基板上的绝缘材料，形成在绝缘材料内的底部电极，沉积在底部电极上方的多个绝缘层，并且其中至少一个用作中间绝缘层 层。 在中间绝缘层上方的绝缘层中限定通孔。 创建一个通道用于用牺牲隔离物进行蚀刻。 在中间绝缘层中限定孔。 除去中间绝缘层之上的所有绝缘层，并且剩余的孔的整个填充有相变材料。 在相变材料上形成上电极。