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公开(公告)号：US09135129B2
公开(公告)日：2015-09-15
申请号：US13739732
申请日：2013-01-11
CPC分类号： G06F11/2205 , G06F7/58
摘要： A method and apparatus for testing operation of a random number generator (RNG) testing circuit are provided. In accordance with at least one embodiment, a first RNG output value obtained from a RNG is stored in a first register. In response to activation of a test mode to simulate a faulty RNG, the first RNG output value is stored in a second register. The first RNG output value in the first register is compared to the first RNG output value in the second register. In response to the comparing, a RNG failure signal is provided at a RNG testing circuit output of the RNG testing circuit. In accordance with at least one embodiment, sequential and combinational logic can simulate a faulty RNG. Accordingly, simulation of a faulty RNG may be performed to test a RNG testing circuit even when the RNG is not faulty.
摘要翻译： 提供了一种用于测试随机数发生器（RNG）测试电路的操作的方法和装置。 根据至少一个实施例，从RNG获得的第一RNG输出值被存储在第一寄存器中。 响应激活测试模式来模拟有故障的RNG，第一个RNG输出值存储在第二个寄存器中。 第一个寄存器中的第一个RNG输出值与第二个寄存器中的第一个RNG输出值进行比较。 响应于比较，在RNG测试电路的RNG测试电路输出端提供RNG故障信号。 根据至少一个实施例，顺序和组合逻辑可以模拟错误的RNG。 因此，即使当RNG没有故障时，也可以对RNG测试电路进行模拟，以测试RNG测试电路。
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公开(公告)号：US20140201252A1
公开(公告)日：2014-07-17
申请号：US13739732
申请日：2013-01-11
IPC分类号： G06F7/58
CPC分类号： G06F11/2205 , G06F7/58
摘要： A method and apparatus for testing operation of a random number generator (RNG) testing circuit are provided. In accordance with at least one embodiment, a first RNG output value obtained from a RNG is stored in a first register. In response to activation of a test mode to simulate a faulty RNG, the first RNG output value is stored in a second register. The first RNG output value in the first register is compared to the first RNG output value in the second register. In response to the comparing, a RNG failure signal is provided at a RNG testing circuit output of the RNG testing circuit. In accordance with at least one embodiment, sequential and combinational logic can simulate a faulty RNG. Accordingly, simulation of a faulty RNG may be performed to test a RNG testing circuit even when the RNG is not faulty.
摘要翻译： 提供了一种用于测试随机数发生器（RNG）测试电路的操作的方法和装置。 根据至少一个实施例，从RNG获得的第一RNG输出值被存储在第一寄存器中。 响应激活测试模式来模拟有故障的RNG，第一个RNG输出值存储在第二个寄存器中。 第一个寄存器中的第一个RNG输出值与第二个寄存器中的第一个RNG输出值进行比较。 响应于比较，在RNG测试电路的RNG测试电路输出端提供RNG故障信号。 根据至少一个实施例，顺序和组合逻辑可以模拟错误的RNG。 因此，即使当RNG没有故障时，也可以对RNG测试电路进行模拟，以测试RNG测试电路。
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公开(公告)号：US09424200B2
公开(公告)日：2016-08-23
申请号：US13842516
申请日：2013-03-15
CPC分类号： G06F12/1009 , G06F21/57 , G06F21/64
摘要： A run-time integrity checking (RTIC) method compatible with memory having at least portions that store data that is changed over time or at least portions configured as virtual memory is provided. For example, the method may comprise storing a table of page entries and accessing the table of page entries by, as an example, an operating system or, as another example, a hypervisor to perform RTIC on memory in which, as an example, an operating system, as another example, a hypervisor, or, as yet another example, application software is stored. The table may, for example, be stored in secure memory or in external memory. The page entry comprises a hash value for the page and a hash valid indicator indicating the validity status of the hash value. The page entry may further comprise a residency indicator indicating a residency status of the memory page.
摘要翻译： 提供与具有存储器的运行时完整性检查（RTIC）方法兼容，该存储器具有至少部分存储随时间改变的数据或至少部分被配置为虚拟存储器的数据。 例如，该方法可以包括通过作为示例的操作系统存储页面条目表和访问页面条目，或者作为另一示例，管理程序来在存储器上执行RTIC，其中作为示例，例如， 操作系统，作为另一示例，管理程序，或者作为另一示例存储应用软件。 该表可以例如存储在安全存储器或外部存储器中。 页面条目包括页面的哈希值和指示哈希值的有效性状态的散列有效指示符。 页面条目还可以包括指示存储器页面的驻留状态的驻留指示符。
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4.发明授权Systems with multiple port random number generators and methods of their operation 有权具有多端口随机数发生器的系统及其操作方法公开(公告)号：US09092283B2
公开(公告)日：2015-07-28
申请号：US13436052
申请日：2012-03-30
IPC分类号： G06F7/58
CPC分类号： G06F7/58
摘要： Methods and systems for producing random numbers include a random number generator with a first port and a second port. The first port is configured to receive a first type of random data request, and the random number generator is configured to generate first random data while the first type of request is asserted on the first port. The second port is configured to receive a second type of random data request, and the random number generator is configured to generate only a specified length of second random data in response to receiving the second type of request on the second port. An embodiment of a system also includes a data structure configured to store multiple random values, which are derived from the first random data generated by the random number generator in response to the first type of random data request.
摘要翻译： 用于产生随机数的方法和系统包括具有第一端口和第二端口的随机数发生器。 第一端口被配置为接收第一类型的随机数据请求，并且随机数发生器被配置为在第一端口上确认第一类型的请求时生成第一随机数据。 第二端口被配置为接收第二类型的随机数据请求，并且随机数发生器被配置为响应于在第二端口上接收到第二类型的请求而仅生成指定长度的第二随机数据。 系统的实施例还包括被配置为存储多个随机值的数据结构，所述多个随机值响应于第一类型的随机数据请求从随机数生成器生成的第一随机数据导出。
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5.发明授权Queued interface devices, multi-core peripheral systems, and methods for sharing a peripheral in a multi-core system 有权排队接口设备，多核外设系统以及在多核系统中共享外设的方法公开(公告)号：US07512723B2
公开(公告)日：2009-03-31
申请号：US11647653
申请日：2006-12-29
IPC分类号： G06F3/00
CPC分类号： G06F13/364
摘要： A queued interface device configured to communicate with a peripheral includes a first interface configured to receive and store a first set of peripheral requests from a first core, a second interface configured to receive and store a second set of peripheral requests from a second core, and an arbitrator coupled to the first interface and the second interface. The arbitrator, which may include multiple sets of registers to store the peripheral requests, is configured to selectively send the first set of peripheral requests and the second set of peripheral requests to the peripheral. The peripheral simultaneously appears as a dedicated peripheral for both the first and second cores.
摘要翻译： 配置为与外围设备通信的排队接口设备包括被配置为从第一核心接收和存储第一组外围设备请求的第一接口，被配置为从第二核心接收和存储第二组外围设备请求的第二接口，以及 耦合到所述第一接口和所述第二接口的仲裁器。 仲裁器可以包括用于存储外围请求的多组寄存器，其被配置为选择性地向外围设备发送第一组外设请求和第二组外设请求。 外围设备同时显示为第一和第二核心的专用外围设备。
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6.发明申请System-on-a-chip and method for securely transferring data on a system-on-a-chip 审中-公开片上系统芯片和方法，用于在片上系统中安全传输数据公开(公告)号：US20080028226A1
公开(公告)日：2008-01-31
申请号：US11496872
申请日：2006-07-31
IPC分类号： H04L9/00
CPC分类号： H04L63/08
摘要： A system-on-a-chip and method for securely transferring data can include a trusted master; a first trusted slave; an untrusted component; and a common bus coupling the trusted master, the first trusted slave, and the untrusted component, In response to an initiation by a host, the trusted master provides a first access request to request a first data transfer with the first trusted slave, and wherein the trusted master does not perform the first data transfer until authentication of the first trusted slave.
摘要翻译： 用于安全地传输数据的片上系统和方法可以包括可信主机; 第一个信任的奴隶; 不可信的组件; 以及耦合所述可信主机，所述第一受信任从机和所述不可信组件的公共总线。响应于主机的启动，所述可信主机提供第一访问请求以请求与所述第一受信任从机的第一数据传输，并且其中 受信任主机在第一个受信赖从站的认证之前不执行第一个数据传输。
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公开(公告)号：US09436248B2
公开(公告)日：2016-09-06
申请号：US13956118
申请日：2013-07-31
摘要： A semiconductor device includes a processing system including a section of power domain circuitry and a section of coin cell power domain circuitry. The coin cell power domain circuitry is configured to, when power is initially provided to the coin cell power domain circuitry, using power provided by a power management circuit as feedback to determine that the power management circuit provides the power in response to a power request signal being a toggle signal, and determine that the power management circuit provides the power in response to the power request signal being a pulse signal.
摘要翻译： 半导体器件包括处理系统，该处理系统包括一部分功率域电路和一部分硬币电池功率域电路。 硬币电池功率域电路被配置为当使用由功率管理电路提供的功率作为反馈来最初向硬币电池功率域电路供电时，确定功率管理电路响应功率请求信号而提供功率 作为触发信号，并且确定功率管理电路响应于作为脉冲信号的功率请求信号而提供功率。
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公开(公告)号：US20080162745A1
公开(公告)日：2008-07-03
申请号：US11647653
申请日：2006-12-29
IPC分类号： G06F3/00
CPC分类号： G06F13/364
摘要： A queued interface device configured to communicate with a peripheral includes a first interface configured to receive and store a first set of peripheral requests from a first core, a second interface configured to receive and store a second set of peripheral requests from a second core, and an arbitrator coupled to the first interface and the second interface. The arbitrator, which may include multiple sets of registers to store the peripheral requests, is configured to selectively send the first set of peripheral requests and the second set of peripheral requests to the peripheral. The peripheral simultaneously appears as a dedicated peripheral for both the first and second cores.
摘要翻译： 配置为与外围设备通信的排队接口设备包括被配置为从第一核心接收和存储第一组外围设备请求的第一接口，被配置为从第二核心接收和存储第二组外围设备请求的第二接口，以及 耦合到所述第一接口和所述第二接口的仲裁器。 仲裁器可以包括用于存储外围请求的多组寄存器，其被配置为选择性地向外围设备发送第一组外设请求和第二组外设请求。 外围设备同时显示为第一和第二核心的专用外围设备。
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公开(公告)号：US20150039916A1
公开(公告)日：2015-02-05
申请号：US13956118
申请日：2013-07-31
IPC分类号： G06F1/26
摘要： A semiconductor device includes a processing system including a section of power domain circuitry and a section of coin cell power domain circuitry. The coin cell power domain circuitry is configured to, when power is initially provided to the coin cell power domain circuitry, using power provided by a power management circuit as feedback to determine that the power management circuit provides the power in response to a power request signal being a toggle signal, and determine that the power management circuit provides the power in response to the power request signal being a pulse signal.
摘要翻译： 半导体器件包括处理系统，该处理系统包括一部分功率域电路和一部分硬币电池功率域电路。 硬币电池功率域电路被配置为当使用由功率管理电路提供的功率作为反馈来最初向硬币电池功率域电路供电时，确定功率管理电路响应功率请求信号而提供功率 作为触发信号，并且确定功率管理电路响应于作为脉冲信号的功率请求信号而提供功率。
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公开(公告)号：US20140281354A1
公开(公告)日：2014-09-18
申请号：US13842516
申请日：2013-03-15
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F21/57 , G06F21/64
摘要： A run-time integrity checking (RTIC) method compatible with memory having at least portions that store data that is changed over time or at least portions configured as virtual memory is provided. For example, the method may comprise storing a table of page entries and accessing the table of page entries by, as an example, an operating system or, as another example, a hypervisor to perform RTIC on memory in which, as an example, an operating system, as another example, a hypervisor, or, as yet another example, application software is stored. The table may, for example, be stored in secure memory or in external memory. The page entry comprises a hash value for the page and a hash valid indicator indicating the validity status of the hash value. The page entry may further comprise a residency indicator indicating a residency status of the memory page.
摘要翻译： 提供与具有存储器的运行时完整性检查（RTIC）方法兼容，该存储器具有至少部分存储随时间改变的数据或至少部分被配置为虚拟存储器的数据。 例如，该方法可以包括通过作为示例的操作系统存储页面条目表和访问页面条目表，或者作为另一示例，管理程序来在存储器上执行RTIC，其中作为示例，例如， 操作系统，作为另一示例，管理程序，或者作为另一示例存储应用软件。 该表可以例如存储在安全存储器或外部存储器中。 页面条目包括页面的哈希值和指示哈希值的有效性状态的散列有效指示符。 页面条目还可以包括指示存储器页面的驻留状态的驻留指示符。
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