摘要:
A phased-array receiver that may be effectively implemented on a silicon substrate. A receiver includes multiple radio frequency (RF) front-ends, each configured to receive a signal with a given delay relative to the others such that the gain of the received signal is highest in a given direction. The receiver also includes a power combination network configured to accept an RF signal from each of the RF front-ends and to pass a combined RF signal to a down-conversion element, where the power distribution network includes a combination of active and passive components. Each RF front-end includes a phase shifter configured to delay the signal in accordance with the given direction and a variable amplifier configured to adjust the gain of the signal.
摘要:
A phased-array receiver that may be effectively implemented on a silicon substrate. A receiver includes multiple radio frequency (RF) front-ends, each configured to receive a signal with a given delay relative to the others such that the gain of the received signal is highest in a given direction. The receiver also includes a power combination network configured to accept an RF signal from each of the RF front-ends and to pass a combined RF signal to a down-conversion element, where the power distribution network includes a combination of active and passive components. Each RF front-end includes a phase shifter configured to delay the signal in accordance with the given direction and a variable amplifier configured to adjust the gain of the signal.
摘要:
A digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.
摘要:
A digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.