公开(公告)号：US20170229442A1

公开(公告)日：2017-08-10

申请号：US15495185

申请日：2017-04-24

Applicant: MediaTek Inc.

Inventor： Chien-Kai HUANG ,  Yuan-Fu CHUNG ,  Bo-Shih HUANG ,  Chang-Tzu WANG

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0296 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/8611

Abstract: A semiconductor device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. The semiconductor device also includes a first doping region formed in a portion of at least one portion of the semiconductor substrate separating the pair of first well regions, and a pair of second doping regions, respectively formed in one of the pair of first well regions, having the first conductivity type. Further, the semiconductor device includes a pair of insulating layers, respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the pair of second doping regions.

公开(公告)号：US20160225755A1

公开(公告)日：2016-08-04

申请号：US14608752

申请日：2015-01-29

Applicant: MediaTek Inc.

Inventor： Chang-Tzu WANG

IPC: H01L27/02 ,  H01L29/04 ,  H01L29/16 ,  H01L29/10

CPC classification number: H01L27/0262 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0266 ,  H01L29/04 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/7436

Abstract: An ESD device disposed on a substrate is provided. The ESD device includes a first well, a second well, a first poly-silicon region, a second poly-silicon region and a first protection layer. The first well has a first conductive type and is disposed on the substrate. The second well has a second conductive type, is disposed on the substrate and is adjacent to the first well. The first poly-silicon region is disposed on the first well. The second poly-silicon region is disposed on the second well. The first protection layer covers portions of the first well, the second well, the first poly-silicon region and the second poly-silicon region. There is no doping region in the portions of the first well and the second well which are covered by the first protection layer and between the first poly-silicon region and the second poly-silicon region.

Abstract translation: 提供了设置在基板上的ESD装置。 ESD器件包括第一阱，第二阱，第一多晶硅区，第二多晶硅区和第一保护层。 第一阱具有第一导电类型并且设置在基板上。 第二阱具有第二导电类型，设置在衬底上并与第一阱相邻。 第一多晶硅区域设置在第一阱上。 第二多晶硅区域设置在第二阱上。 第一保护层覆盖第一阱，第二阱，第一多晶硅区和第二多晶硅区的部分。 在第一阱和第二阱的部分中没有掺杂区域被第一保护层覆盖，并且在第一多晶硅区域和第二多晶硅区域之间。

公开(公告)号：US20160141285A1

公开(公告)日：2016-05-19

申请号：US14884981

申请日：2015-10-16

Applicant: MediaTek Inc.

Inventor： Chien-Kai HUANG ,  Yuan-Fu CHUNG ,  Bo-Shih HUANG ,  Chang-Tzu WANG

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L27/0296 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/8611

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the ESD protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type. Moreover, the ESD protection device further includes a pair of second doping regions respectively formed in one of the first well regions, having the first conductivity type, and a pair of insulating layers respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the second doping regions.

Abstract translation: 静电放电（ESD）保护装置包括半导体衬底和形成在半导体衬底中的一对第一阱区，其中该一对第一阱区具有第一导电类型并由半导体衬底的至少一部分分隔开。 此外，ESD保护装置还包括形成在半导体衬底的至少一部分的一部分中的第一掺杂区域，该半导体衬底的一部分与第一导电类型相反地具有第二导电类型。 此外，ESD保护装置还包括分别形成在具有第一导电类型的第一阱区域中的一个中的一对第二掺杂区域和分别形成在半导体衬底的一部分上以覆盖部分的一对绝缘层 第一掺杂区和第二掺杂区中的一个。

公开(公告)号：US20160372468A1

公开(公告)日：2016-12-22

申请号：US15122379

申请日：2015-05-25

Applicant: MEDIATEK INC.

Inventor： Chang-Tzu WANG ,  Bo-Shih HUANG

IPC: H01L27/088 ,  H01L23/535

CPC classification number: H01L27/0886 ,  H01L23/535 ,  H01L27/027 ,  H01L29/785

Abstract: The invention provides a semiconductor device. The semiconductor device includes a fin field effect transistor (finFET) array including finFET units. Each of the finFET units includes a substrate having a fin along a first direction. A first metal strip pattern and a second metal strip pattern are formed on the fin, extending along a second direction that is different from the first direction. The first and second metal strip patterns are conformally formed on opposite sidewalls and a top surface of the fin, respectively. A first contact and a second contact are formed on the fin. The first and second metal strip patterns are disposed between the first and second contacts. A first dummy contact is formed on the fin, sandwiched between the first and second metal strip patterns.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括鳍状场效应晶体管（finFET）阵列，其包括finFET单元。 每个finFET单元包括具有沿着第一方向的鳍片的衬底。 第一金属带图案和第二金属带图案形成在翅片上，沿着与第一方向不同的第二方向延伸。 第一和第二金属带图案分别共形地形成在翅片的相对侧壁和顶表面上。 在翅片上形成第一接触和第二接触。 第一和第二金属带图案设置在第一和第二触点之间。 第一虚拟接触件形成在翅片上，夹在第一和第二金属带状图案之间。