公开(公告)号：US20140203368A1

公开(公告)日：2014-07-24

申请号：US14108559

申请日：2013-12-17

Applicant: MediaTek Inc.

Inventor： Zheng ZENG ,  Ching-Chung KO ,  Bo-Shih HUANG

IPC: H01L27/02

CPC classification number: H01L29/0619 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

Abstract: The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region. The first metal contact and a second metal contact are separated by a poly pattern or an insulating layer pattern disposed on the first well region.

Abstract translation: 本发明提供一种静电放电（ESD）保护装置。 ESD保护器件包括具有有源区的半导体衬底。 在有源区中形成具有第一导电类型的第一阱区。 具有第一导电类型的第一掺杂区形成在第一阱区中。 第一金属触点设置在第一掺杂区域上。 第二金属触点设置在有源区上，连接到第一阱区。 第一金属触点和第二金属触点被设置在第一阱区域上的多晶型图案或绝缘层图案分开。

公开(公告)号：US20170229442A1

公开(公告)日：2017-08-10

申请号：US15495185

申请日：2017-04-24

Applicant: MediaTek Inc.

Inventor： Chien-Kai HUANG ,  Yuan-Fu CHUNG ,  Bo-Shih HUANG ,  Chang-Tzu WANG

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0296 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/8611

Abstract: A semiconductor device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. The semiconductor device also includes a first doping region formed in a portion of at least one portion of the semiconductor substrate separating the pair of first well regions, and a pair of second doping regions, respectively formed in one of the pair of first well regions, having the first conductivity type. Further, the semiconductor device includes a pair of insulating layers, respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the pair of second doping regions.

公开(公告)号：US20150124362A1

公开(公告)日：2015-05-07

申请号：US14591254

申请日：2015-01-07

Applicant: MediaTek Inc

Inventor： Bo-Shih HUANG ,  Tsung-Ming CHEN ,  Yuan-Hung CHUNG

IPC: H02H3/20

CPC classification number: H02H3/20 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line, wherein no ESD current flows through the impedance device when an ESD event occurs at the pad.

Abstract translation: 提供静电放电（ESD）保护电路。 ESD保护电路包括耦合在焊盘和电源线之间的阻抗装置以及耦合在焊盘和接地线之间的夹紧单元，其中当在焊盘处发生ESD事件时，ESD电流不流过阻抗器件。

公开(公告)号：US20140362482A1

公开(公告)日：2014-12-11

申请号：US13911645

申请日：2013-06-06

Applicant: MediaTek Inc.

Inventor： Bo-Shih HUANG ,  Tzung-Han WU ,  Chi-Yao YU

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An ESD (Electrostatic discharge) structure for enhancing robustness of CDM (Charge Device Model) at least includes an input stage. The input stage includes an input pad, a first ESD clamp circuit, a second ESD clamp circuit, a resistor, and a transistor. The input pad is configured to receive an input signal. The first ESD clamp circuit is coupled between the input pad and a work voltage. The second ESD clamp circuit is coupled between the input pad and a ground voltage. The first clamp circuit and the second clamp circuit are capable of bypassing an electrostatic current. The transistor has a first source/drain, a second source/drain, a gate coupled to the input pad, and a bulk coupled through the resistor to the work voltage or the ground voltage.

Abstract translation: 用于增强CDM（充电装置型号）的鲁棒性的ESD（静电放电）结构至少包括输入级。 输入级包括输入焊盘，第一ESD钳位电路，第二ESD钳位电路，电阻器和晶体管。 输入焊盘被配置为接收输入信号。 第一ESD钳位电路耦合在输入焊盘和工作电压之间。 第二ESD钳位电路耦合在输入焊盘和接地电压之间。 第一钳位电路和第二钳位电路能够绕过静电电流。 晶体管具有第一源极/漏极，第二源极/漏极，耦合到输入焊盘的栅极和通过电阻器耦合到工作电压或接地电压的体积。

公开(公告)号：US20240243120A1

公开(公告)日：2024-07-18

申请号：US18544764

申请日：2023-12-19

Applicant: MEDIATEK INC.

Inventor： Han-Sheng HUANG ,  Bo-Shih HUANG

IPC: H01L27/02

CPC classification number: H01L27/027

Abstract: Electrostatic discharge (ESD) protection structures are provided. A first N-type well region is formed over a P-type semiconductor substrate. First P-type well region and second N-type well region are formed over the first N-type well region. A plurality of first device areas are formed over the first P-type well region. Each first device area includes a plurality of P-type fins extending in a first direction. The P-type fins are divided into a plurality of first groups in each of the first device areas. A second device area is formed over the first P-type well region, and includes a plurality of N-type fins extending in the first direction and surrounded by the first device areas. When an ESD event is present, an ESD current flows sequentially through the P-type fins, the first P-type well region and the N-type fins.

公开(公告)号：US20160372468A1

公开(公告)日：2016-12-22

申请号：US15122379

申请日：2015-05-25

Applicant: MEDIATEK INC.

Inventor： Chang-Tzu WANG ,  Bo-Shih HUANG

IPC: H01L27/088 ,  H01L23/535

CPC classification number: H01L27/0886 ,  H01L23/535 ,  H01L27/027 ,  H01L29/785

Abstract: The invention provides a semiconductor device. The semiconductor device includes a fin field effect transistor (finFET) array including finFET units. Each of the finFET units includes a substrate having a fin along a first direction. A first metal strip pattern and a second metal strip pattern are formed on the fin, extending along a second direction that is different from the first direction. The first and second metal strip patterns are conformally formed on opposite sidewalls and a top surface of the fin, respectively. A first contact and a second contact are formed on the fin. The first and second metal strip patterns are disposed between the first and second contacts. A first dummy contact is formed on the fin, sandwiched between the first and second metal strip patterns.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括鳍状场效应晶体管（finFET）阵列，其包括finFET单元。 每个finFET单元包括具有沿着第一方向的鳍片的衬底。 第一金属带图案和第二金属带图案形成在翅片上，沿着与第一方向不同的第二方向延伸。 第一和第二金属带图案分别共形地形成在翅片的相对侧壁和顶表面上。 在翅片上形成第一接触和第二接触。 第一和第二金属带图案设置在第一和第二触点之间。 第一虚拟接触件形成在翅片上，夹在第一和第二金属带状图案之间。

公开(公告)号：US20150171072A1

公开(公告)日：2015-06-18

申请号：US14630733

申请日：2015-02-25

Applicant: MediaTek Inc.

Inventor： Zheng ZENG ,  Ching-Chung KO ,  Bo-Shih HUANG

IPC: H01L27/02 ,  H01L29/47 ,  H01L29/872

CPC classification number: H01L29/0619 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

Abstract: The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region, a first well region having a first conductive type formed in the active region, a first doped region having the first conductive type formed in the first well region, a first metal contact disposed on the first doped region, and a second metal contact disposed on the active region, connecting to the first well region, wherein no doped region is formed between the second metal contact and the first well region.

Abstract translation: 本发明提供一种静电放电（ESD）保护装置。 ESD保护器件包括具有有源区的半导体衬底，在有源区中形成的具有第一导电类型的第一阱区，形成在第一阱区中的第一导电类型的第一掺杂区，设置在第一阱区上的第一金属触点 所述第一掺杂区域和设置在所述有源区上的第二金属触点连接到所述第一阱区域，其中在所述第二金属触点和所述第一阱区域之间没有形成掺杂区域。

公开(公告)号：US20170200783A1

公开(公告)日：2017-07-13

申请号：US15469846

申请日：2017-03-27

Applicant: MediaTek Inc.

Inventor： Zheng ZENG ,  Ching-Chung KO ,  Bo-Shih HUANG

IPC: H01L29/06 ,  H01L29/872 ,  H01L29/78 ,  H01L27/02 ,  H01L29/47

CPC classification number: H01L29/0619 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

Abstract: The invention provides an electrostatic discharge (ESD) protection device formed by a Schottky diode. An exemplary embodiment of an ESD protection device comprises a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first heavily doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region without through any heavily doped region being located therebetween, wherein the first metal contact and the second metal contact are separated by a polysilicon pattern disposed on the first well region.

公开(公告)号：US20160141285A1

公开(公告)日：2016-05-19

申请号：US14884981

申请日：2015-10-16

Applicant: MediaTek Inc.

Inventor： Chien-Kai HUANG ,  Yuan-Fu CHUNG ,  Bo-Shih HUANG ,  Chang-Tzu WANG

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L27/0296 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/8611

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the ESD protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type. Moreover, the ESD protection device further includes a pair of second doping regions respectively formed in one of the first well regions, having the first conductivity type, and a pair of insulating layers respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the second doping regions.

Abstract translation: 静电放电（ESD）保护装置包括半导体衬底和形成在半导体衬底中的一对第一阱区，其中该一对第一阱区具有第一导电类型并由半导体衬底的至少一部分分隔开。 此外，ESD保护装置还包括形成在半导体衬底的至少一部分的一部分中的第一掺杂区域，该半导体衬底的一部分与第一导电类型相反地具有第二导电类型。 此外，ESD保护装置还包括分别形成在具有第一导电类型的第一阱区域中的一个中的一对第二掺杂区域和分别形成在半导体衬底的一部分上以覆盖部分的一对绝缘层 第一掺杂区和第二掺杂区中的一个。

公开(公告)号：US20130114172A1

公开(公告)日：2013-05-09

申请号：US13662851

申请日：2012-10-29

Applicant: MEDIATEK INC.

Inventor： Bo-Shih HUANG ,  Tsung-Ming CHEN ,  Yuan-Hung CHUNG

IPC: H02H3/20

CPC classification number: H02H3/20 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line.

Abstract translation: 提供静电放电（ESD）保护电路。 ESD保护电路包括耦合在焊盘和电源线之间的阻抗装置以及耦合在焊盘和接地线之间的夹紧单元。