公开(公告)号：US09690365B2

公开(公告)日：2017-06-27

申请号：US15138462

申请日：2016-04-26

Applicant: MediaTek Inc.

Inventor： Hugh Thomas Mair ,  Yi-Te Chiu ,  Che-Wei Wu ,  Lee-Kee Yong ,  Chia-Wei Wang ,  Cheng-Hsing Chien ,  Uming Ko

IPC: G11C7/22 ,  G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/172

Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

公开(公告)号：US20160320821A1

公开(公告)日：2016-11-03

申请号：US15138462

申请日：2016-04-26

Applicant: MediaTek Inc.

Inventor： Hugh Thomas Mair ,  Yi-Te Chiu ,  Che-Wei Wu ,  Lee-Kee Yong ,  Chia-Wei Wang ,  Cheng-Hsing Chien ,  Uming Ko

IPC: G06F1/28

CPC classification number: G06F1/3296 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/172

Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

Abstract translation: 处理装置为其存储单元阵列和逻辑电路执行双轨功率均衡。 存储单元阵列通过第一开关耦合到第一电源轨，以接收第一电压电平。 逻辑电路通过第二开关耦合到第二电源轨，以接收不同于第一电压电平的第二电压电平。 处理装置还包括耦合到至少第二电力轨的功率开关，并且被操作以使得能够均衡提供给存储单元阵列和逻辑电路的电压。