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    Dual-Rail Power Equalizer
    2.
    发明申请
    Dual-Rail Power Equalizer 有权
    双轨功率均衡器

    公开(公告)号：US20160320821A1

    公开(公告)日：2016-11-03

    申请号：US15138462

    申请日：2016-04-26

    Applicant: MediaTek Inc.

    Inventor： Hugh Thomas Mair ,  Yi-Te Chiu ,  Che-Wei Wu ,  Lee-Kee Yong ,  Chia-Wei Wang ,  Cheng-Hsing Chien ,  Uming Ko

    IPC: G06F1/28

    CPC classification number: G06F1/3296 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/172

    Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

    Abstract translation: 处理装置为其存储单元阵列和逻辑电路执行双轨功率均衡。 存储单元阵列通过第一开关耦合到第一电源轨，以接收第一电压电平。 逻辑电路通过第二开关耦合到第二电源轨，以接收不同于第一电压电平的第二电压电平。 处理装置还包括耦合到至少第二电力轨的功率开关，并且被操作以使得能够均衡提供给存储单元阵列和逻辑电路的电压。

    METHOD FOR INCLUDING DECOUPLING CAPACITORS INTO SEMICONDUCTOR CIRCUIT HAVING LOGIC CIRCUIT THEREIN AND SEMICONDUCTOR CIRCUIT THEREOF
    3.
    发明申请
    METHOD FOR INCLUDING DECOUPLING CAPACITORS INTO SEMICONDUCTOR CIRCUIT HAVING LOGIC CIRCUIT THEREIN AND SEMICONDUCTOR CIRCUIT THEREOF 审中-公开
    将解耦电容器放入具有逻辑电路的半导体电路及其半导体电路的方法

    公开(公告)号：US20150001675A1

    公开(公告)日：2015-01-01

    申请号：US14490690

    申请日：2014-09-19

    Applicant: MEDIATEK INC.

    Inventor： Tien-Chang Chang ,  Ming-Tzong Yang ,  Tao Cheng ,  Cheng-Hsing Chien ,  Hsin-Hsin Hsiao

    IPC: H01L49/02 ,  H01L27/06

    CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0811 ,  H01L29/94

    Abstract: A semiconductor circuit comprises a first and a second logic circuit, a first and a second decoupling capacitor. The first decoupling capacitor is arranged in a first area around the first logic circuit and the second decoupling capacitor is arranged in a second area around the second logic circuit. Wherein, the first area is larger than the second area, a gate oxide thickness of the first decoupling capacitor is larger than a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit. Further, the first and second decoupling capacitors are designed without trench.

    Abstract translation: 半导体电路包括第一和第二逻辑电路，第一和第二去耦电容器。 第一去耦电容器布置在第一逻辑电路周围的第一区域中，并且第二去耦电容器布置在第二逻辑电路周围的第二区域中。 其中，第一区域大于第二区域，第一去耦电容器的栅极氧化物厚度大于第二去耦电容器的栅极氧化物厚度，并且第一区域和第一逻辑电路之间的距离短于第 第二区域与第二逻辑电路之间的距离。 此外，第一和第二去耦电容器被设计成没有沟槽。

    METHOD FOR INCLUDING DECOUPLING CAPACITORS INTO SEMICONDUCTOR CIRCUIT HAVING LOGIC CIRCUIT THEREIN AND SEMICONDUCTOR CIRCUIT THEREOF
    4.
    发明申请
    METHOD FOR INCLUDING DECOUPLING CAPACITORS INTO SEMICONDUCTOR CIRCUIT HAVING LOGIC CIRCUIT THEREIN AND SEMICONDUCTOR CIRCUIT THEREOF 审中-公开
    将解耦电容器放入具有逻辑电路的半导体电路及其半导体电路的方法

    公开(公告)号：US20140175608A1

    公开(公告)日：2014-06-26

    申请号：US14190058

    申请日：2014-02-25

    Applicant: MEDIATEK INC.

    Inventor： Tien-Chang Chang ,  Ming-Tzong Yang ,  Tao Cheng ,  Cheng-Hsing Chien ,  Hsin-Hsin Hsiao

    IPC: H01L49/02

    CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0811

    Abstract: A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit.

    Abstract translation: 一种用于将去耦电容器包括至其中至少具有逻辑电路的半导体电路的方法包括：将第一去耦电容器和第二去耦电容器分别布置在逻辑电路周围的第一区域和第二区域中，其中栅极氧化物厚度 第一去耦电容器与第二去耦电容器的栅极氧化物厚度不同，并且第一区域和第一逻辑电路之间的距离小于第二区域和第二逻辑电路之间的距离。

    Flip-flop for low swing clock signal
    5.
    发明授权
    Flip-flop for low swing clock signal 有权
    低电平时钟信号触发器

    公开(公告)号：US08717079B2

    公开(公告)日：2014-05-06

    申请号：US13908700

    申请日：2013-06-03

    Applicant: MediaTek Inc.

    Inventor： Cheng-Hsing Chien ,  Yung-Chieh Yu ,  Jia-Yi Xu

    IPC: H03K3/356 ,  H03K3/00

    CPC classification number: H03K3/356147 ,  H03K3/012 ,  H03K3/356156

    Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

    Abstract translation: 本发明提供一种触发器。 在一个实施例中，触发器接收低摆频时钟信号，并且包括第一NMOS晶体管，第一锁存电路，第二NMOS晶体管和第二锁存电路。 低摆频时钟信号被反相以获得反相的低摆频时钟信号。 第一NMOS晶体管耦合在接收节点和第一节点之间，并且具有耦合到反相低摆频时钟信号的栅极。 第一锁存电路耦合在第一节点和第二节点之间。 第二NMOS晶体管耦合在第二节点和第三节点之间。 第二锁存电路耦合在第三节点和第四节点之间，并且在第四节点上产生输出信号。

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