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公开(公告)号：US20240312557A1
公开(公告)日：2024-09-19
申请号：US18443347
申请日：2024-02-16
Applicant: MEDIATEK INC.
Inventor： Che-Wei Chou , Ya-Ting Yang , Shu-Lin Lai , Chi-Kai Hsieh , Yi-Ping Kuo , Chi-Hao Hong , Jia-Jing Chen , Yi-Te Chiu , Jiann-Tseng Huang
CPC classification number: G11C29/702 , G11C29/56008 , G11C29/56016
Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.
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公开(公告)号：US20220406373A1
公开(公告)日：2022-12-22
申请号：US17894191
申请日：2022-08-24
Applicant: MEDIATEK INC.
Inventor： Yi-Ping Kuo , Yi-Te Chiu
IPC: G11C11/419
Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.
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公开(公告)号：US20240412779A1
公开(公告)日：2024-12-12
申请号：US18739363
申请日：2024-06-11
Applicant: MEDIATEK INC.
Inventor： Yi-Te Chiu , Ya-Ting Yang , Jia-Jing Chen
IPC: G11C11/418 , G11C5/06
Abstract: A pre-charge system includes a pre-charge circuit and a timing controller circuit. The pre-charge circuit performs time-division pre-charge upon a plurality of bit-line groups of a memory array according to a plurality of pre-charge timing control signals, wherein the memory array includes a plurality of memory cells each coupled to one of the plurality of bit-line groups. The timing controller circuit generates and outputs the plurality of pre-charge timing control signals to the pre-charge circuit.
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公开(公告)号：US10181358B2
公开(公告)日：2019-01-15
申请号：US15492014
申请日：2017-04-20
Applicant: MEDIATEK Inc.
Inventor： Chia-Wei Wang , Shu-Lin Lai , Yi-Te Chiu
Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.
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公开(公告)号：US20210327500A1
公开(公告)日：2021-10-21
申请号：US17210521
申请日：2021-03-24
Applicant: MEDIATEK INC.
Inventor： Yi-Ping Kuo , Yi-Te Chiu
IPC: G11C11/419
Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.
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Patent Agency Ranking
公开(公告)号：US10770161B2
公开(公告)日：2020-09-08
申请号：US16211524
申请日：2018-12-06
Applicant: MEDIATEK Inc.
Inventor： Chia-Wei Wang , Shu-Lin Lai , Yi-Te Chiu
Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.
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公开(公告)号：US09690365B2
公开(公告)日：2017-06-27
申请号：US15138462
申请日：2016-04-26
Applicant: MediaTek Inc.
Inventor： Hugh Thomas Mair , Yi-Te Chiu , Che-Wei Wu , Lee-Kee Yong , Chia-Wei Wang , Cheng-Hsing Chien , Uming Ko
CPC classification number: G06F1/3296 , G06F1/3275 , Y02D10/14 , Y02D10/172
Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.
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公开(公告)号：US11676657B2
公开(公告)日：2023-06-13
申请号：US17210521
申请日：2021-03-24
Applicant: MEDIATEK INC.
Inventor： Yi-Ping Kuo , Yi-Te Chiu
IPC: G11C11/419
CPC classification number: G11C11/419
Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.
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公开(公告)号：US20220366116A1
公开(公告)日：2022-11-17
申请号：US17673755
申请日：2022-02-16
Applicant: MEDIATEK INC.
Inventor： Yu-Tung Chang , Yi-Chun Tsai , Tung-Kai Tsai , Yi-Te Chiu , Shih-Yun Lin , Hung-Ming Chu , Yi-Feng Chen
IPC: G06F30/392
Abstract: An integrated circuit (IC) may include a plurality of functional blocks, and each functional block of the plurality of functional blocks may include hardware circuits, wherein the plurality of functional blocks may include a first functional block. In addition, the first functional block may include a first macro circuit that is positioned within a first sub-region of the first functional block, wherein among multiple sides of the first sub-region, a first side of the first sub-region is closest to a boundary of the first functional block. Additionally, a first intermediate sub-region of the first functional block is positioned between the first side of the first sub-region and the boundary of the first functional block, and there is no tap cell in the first intermediate sub-region of the first functional block.
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公开(公告)号：US20160320821A1
公开(公告)日：2016-11-03
申请号：US15138462
申请日：2016-04-26
Applicant: MediaTek Inc.
Inventor： Hugh Thomas Mair , Yi-Te Chiu , Che-Wei Wu , Lee-Kee Yong , Chia-Wei Wang , Cheng-Hsing Chien , Uming Ko
IPC: G06F1/28
CPC classification number: G06F1/3296 , G06F1/3275 , Y02D10/14 , Y02D10/172
Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.
Abstract translation: 处理装置为其存储单元阵列和逻辑电路执行双轨功率均衡。 存储单元阵列通过第一开关耦合到第一电源轨，以接收第一电压电平。 逻辑电路通过第二开关耦合到第二电源轨，以接收不同于第一电压电平的第二电压电平。 处理装置还包括耦合到至少第二电力轨的功率开关，并且被操作以使得能够均衡提供给存储单元阵列和逻辑电路的电压。
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