公开(公告)号：US20160217243A1

公开(公告)日：2016-07-28

申请号：US14986275

申请日：2015-12-31

Applicant: MediaTek Inc.

Inventor： Zwei-Mei LEE ,  Bo-Jr HUANG ,  Chi-Jih SHIH ,  Jia-Wei FANG

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5009 ,  G06F17/505 ,  G06F2217/78

Abstract: A method for distributing power in the layout of an integrated circuit is provided. The integrated circuit includes at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block includes a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further includes a low drop out (LDO) regulator.

Abstract translation: 提供了一种用于在集成电路的布局中分配功率的方法。 集成电路包括至少一个宏块。 获得宏块的第一物理布局，其中宏块包括多个标准单元。 根据第一物理布局的IR仿真结果将第一物理布局分成多个分区。 多个电源隔离单元插入分区之间。 根据分区和电源隔离单元获得第二个物理布局。 根据第二物理布局获得宏块的宏放置。 每个分区还包括一个低压降（LDO）调节器。

公开(公告)号：US20150154337A1

公开(公告)日：2015-06-04

申请号：US14546238

申请日：2014-11-18

Applicant: MediaTek Inc.

Inventor： Jia-Wei FANG ,  Chi-Jih SHIH ,  Shen-Yu HUANG

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/40 ,  G06F2217/78 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0612 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed to obtain a total number of micro bumps of the flip-chip according to the information, and obtain a minimum conductance of each of the power pins of the flip-chip according to a bump placement of the micro bumps of the flip-chip. A chip-interposer routing procedure is performed to obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the minimum conductance of the power pins of the flip-chip.

Abstract translation: 提供了一种用于共同设计倒装芯片和插入器的方法。 获得关于倒装芯片的I / O焊盘，电源引脚和IR约束的信息。 根据该信息进行碰撞计划程序以获得倒装芯片的微小凸块的总数，并且根据凸块的凸起位置获得倒装芯片的每个电源引脚的最小电导 倒装芯片。 执行芯片插入器路由过程以根据倒装芯片的电源引脚的最小电导获得倒装芯片的重分布层（RDL）路由和插入器的插入器布线。