公开(公告)号：US20170149423A1

公开(公告)日：2017-05-25

申请号：US15134954

申请日：2016-04-21

Applicant: MediaTek Inc.

Inventor： Bo-Jr HUANG

IPC: H03K5/19 ,  H03K3/03

CPC classification number: H03K5/19 ,  G01R31/2621 ,  G01R31/2644 ,  G01R31/2884 ,  H03K3/0315

Abstract: A ring oscillator includes a plurality of inverters. A closed loop structure is formed by cascading the inverters. The inverter includes at least one sensitive inverter with a diode-connected transistor. A variation in an MOSFET (Metal Oxide SemiconductorField Effect Transistor) threshold voltage of the ring oscillator is detected by analyzing the oscillation frequency of the ring oscillator.

公开(公告)号：US20160320446A1

公开(公告)日：2016-11-03

申请号：US15014664

申请日：2016-02-03

Applicant: MediaTek Inc.

Inventor： Bo-Jr HUANG

IPC: G01R31/28 ,  G01R19/252 ,  G01R19/00

CPC classification number: G01R19/0092 ,  G01R1/203 ,  G01R19/2503 ,  G01R19/252 ,  G01R21/00 ,  G06F1/28

Abstract: A monitor circuit for monitoring a CUT (Circuit Under Test) is provided. The monitor circuit includes a power switch and a current meter. The power switch is coupled between a supply voltage and the CUT. The current meter is coupled in parallel with the power switch. The current meter is configured to detect a current through the CUT.

Abstract translation: 提供了一个用于监视CUT（待测电路）的监视电路。 监视器电路包括电源开关和电流表。 电源开关耦合在电源电压和CUT之间。 电流表与电源开关并联。 当前仪表被配置为检测通过CUT的电流。

公开(公告)号：US20160153840A1

公开(公告)日：2016-06-02

申请号：US14855592

申请日：2015-09-16

Applicant: MediaTek Inc.

Inventor： Bo-Jr HUANG ,  Yi-Feng CHEN ,  Jia-Wei FANG

IPC: G01K7/00 ,  H03K3/011 ,  H02M7/537 ,  H03K3/03

CPC classification number: G01K7/01 ,  G01K7/00 ,  H03K3/0315

Abstract: The invention provides an inverter. The inverter includes a first converter and a second converter. The first converter is coupled between a supply voltage and an output node of the inverter. The second converter is coupled between the output node of the inverter and a ground voltage. The first converter, the second converter, or both include diode-connected transistors. The propagation delay time of the inverter is substantially a linear function of the temperature of the inverter.

Abstract translation: 本发明提供一种逆变器。 逆变器包括第一转换器和第二转换器。 第一转换器耦合在逆变器的电源电压和输出节点之间。 第二转换器耦合在逆变器的输出节点和接地电压之间。 第一转换器，第二转换器或二者都包括二极管连接的晶体管。 逆变器的传播延迟时间基本上是逆变器温度的线性函数。

公开(公告)号：US20160343796A1

公开(公告)日：2016-11-24

申请号：US15158814

申请日：2016-05-19

Applicant: MediaTek Inc.

Inventor： Bo-Jr HUANG ,  Jia-Wei FANG

IPC: H01L49/02

CPC classification number: H01L28/87 ,  H01L23/5223 ,  H01L28/88

Abstract: A capacitor structure includes first and second interdigitated conductive elements formed over different portions of a semiconductor substrate, and a dielectric layer formed between the first and second interdigitated conductive elements. The first interdigitated conductive element that is formed includes a first base portion and a plurality of first protrusion portions. The second interdigitated conductive element includes a second base portion and a plurality of second protrusion portions. The second protrusion portions of the second interdigitated conductive element are interleaved with the first protrusion portions of the first interdigitated conductive element.

Abstract translation: 电容器结构包括形成在半导体衬底的不同部分上的第一和第二交叉导电元件，以及形成在第一和第二叉指导电元件之间的电介质层。 所形成的第一交错导电元件包括​​第一基部和多个第一突出部。 第二交叉导电元件包括​​第二基部和多个第二突出部。 第二交错导电元件的第二突出部分与第一交叉导电元件的第一突出部分交错。

公开(公告)号：US20160217243A1

公开(公告)日：2016-07-28

申请号：US14986275

申请日：2015-12-31

Applicant: MediaTek Inc.

Inventor： Zwei-Mei LEE ,  Bo-Jr HUANG ,  Chi-Jih SHIH ,  Jia-Wei FANG

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5009 ,  G06F17/505 ,  G06F2217/78

Abstract: A method for distributing power in the layout of an integrated circuit is provided. The integrated circuit includes at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block includes a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further includes a low drop out (LDO) regulator.

Abstract translation: 提供了一种用于在集成电路的布局中分配功率的方法。 集成电路包括至少一个宏块。 获得宏块的第一物理布局，其中宏块包括多个标准单元。 根据第一物理布局的IR仿真结果将第一物理布局分成多个分区。 多个电源隔离单元插入分区之间。 根据分区和电源隔离单元获得第二个物理布局。 根据第二物理布局获得宏块的宏放置。 每个分区还包括一个低压降（LDO）调节器。

公开(公告)号：US20160156354A1

公开(公告)日：2016-06-02

申请号：US14926775

申请日：2015-10-29

Applicant: MediaTek Inc.

Inventor： Bo-Jr HUANG ,  Jia-Wei FANG

IPC: H03K19/003 ,  H03K19/20 ,  H03K17/22 ,  H03K5/14 ,  G06F1/24

CPC classification number: H03K19/00361 ,  G06F1/24 ,  H03K5/14 ,  H03K17/223 ,  H03K19/20

Abstract: A sensing circuit includes a delay chain and a decoder. The delay chain includes at least one delay unit, at least one cascading switch, and at least one feedback switch. The delay unit generates a delay signal according to an input signal and a reset signal. The cascading switch selectively passes the delay signal according to a control signal. The feedback switch selectively forms a feedback path of the delay unit according to the control signal. The decoder generates an output signal according to the delay signal. The delay unit is supplied by a work voltage. If the work voltage has noise, the noise will be detectable by analyzing the output signal of the decoder.

Abstract translation: 感测电路包括延迟链和解码器。 延迟链包括至少一个延迟单元，至少一个级联开关和至少一个反馈开关。 延迟单元根据输入信号和复位信号生成延迟信号。 级联开关根据控制信号选择性地传递延迟信号。 反馈开关根据控制信号选择性地形成延迟单元的反馈路径。 解码器根据延迟信号产生输出信号。 延迟单元由工作电压提供。 如果工作电压具有噪声，则可以通过分析解码器的输出信号来检测噪声。