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31 条记录 (耗时 0.017 秒)

    Memory controller, memory module and memory system
    1.
    发明授权
    Memory controller, memory module and memory system 有权

    公开(公告)号：US10083728B2

    公开(公告)日：2018-09-25

    申请号：US14324228

    申请日：2014-07-06

    申请人： MEDIATEK INC.

    发明人： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Pin Chen

    IPC分类号： G06F12/00 ,  G11C8/12 ,  G06F13/16

    CPC分类号： G11C8/12 ,  G06F12/00 ,  G06F13/1668

    摘要： A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

    METHOD FOR PERFORMING PHASE SHIFT CONTROL FOR TIMING RECOVERY IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS
    3.
    发明申请
    METHOD FOR PERFORMING PHASE SHIFT CONTROL FOR TIMING RECOVERY IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS 有权
    用于执行电子设备中的时序恢复的相位移动控制的方法及相关装置

    公开(公告)号：US20160308665A1

    公开(公告)日：2016-10-20

    申请号：US15194509

    申请日：2016-06-27

    申请人： MEDIATEK INC.

    发明人： Yan-Bin Luo ,  Bo-Jiun Chen ,  Ke-Chung Wu ,  Yi-Chieh Huang

    IPC分类号： H04L7/00 ,  H03F3/45 ,  H03L7/081 ,  H04L7/033 ,  H03L7/08

    CPC分类号： H04L7/0087 ,  H03F3/45475 ,  H03K3/0322 ,  H03K5/131 ,  H03K2005/00052 ,  H03K2005/00058 ,  H03L7/0807 ,  H03L7/0814 ,  H04L7/0331

    摘要： A method for performing phase shift control for timing recovery in an electronic device and an associated apparatus are provided, where the method includes: generating an output signal of an oscillator, wherein a phase shift of the output signal of the oscillator is controlled by selectively combining a set of clock signals into the oscillator according to a set of digital control signals, and the set of clock signals is obtained from a clock generator, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals; and performing timing recovery and sampling on a receiver input signal of a receiver in the electronic device according to the output signal of the oscillator to reproduce data from the receiver input signal.

    摘要翻译： 提供一种用于执行电子设备和相关设备中的定时恢复的相移控制的方法，其中该方法包括：产生振荡器的输出信号，其中通过选择性地组合来控制振荡器的输出信号的相移 根据一组数字控制信号将一组时钟信号输入到振荡器中，并且从时钟发生器获得该组时钟信号，其中相移对应于该组数字控制信号，并且该组数字控制信号 携带一组数字加权，用于选择性地混合该组时钟信号; 并根据振荡器的输出信号在电子设备中的接收机的接收机输入信号上执行定时恢复和采样，以从接收机输入信号再现数据。

    Method for performing phase shift control in an electronic device, and associated apparatus
    4.
    发明授权
    Method for performing phase shift control in an electronic device, and associated apparatus 有权
    一种用于在电子设备中执行相移控制的方法，以及相关联的装置

    公开(公告)号：US09473129B2

    公开(公告)日：2016-10-18

    申请号：US14968926

    申请日：2015-12-15

    申请人： MEDIATEK INC.

    发明人： Yan-Bin Luo ,  Bo-Jiun Chen ,  Ke-Chung Wu

    IPC分类号： H03H11/16 ,  H03K5/13 ,  H03K3/03 ,  H03K5/00

    CPC分类号： H03K5/131 ,  H03K3/0322 ,  H03K2005/00052 ,  H03K2005/00058

    摘要： A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital control signals, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital control signals.

    摘要翻译： 提供一种用于在电子设备和相关设备中进行相移控制的方法，其中所述方法包括：获得与一组相位对应的一组时钟信号; 以及通过根据一组数字控制信号选择性地将所述一组时钟信号混合到所述振荡器中来控制振荡器的输出信号的相移，其中所述相移对应于所述一组数字控制信号，并且所述数字集合 控制信号携带一组数字加权，用于选择性地混合该组时钟信号。 更具体地，该方法可以包括：根据该组数字控制信号，将该组时钟信号选择性地混合到振荡器的多个级的特定级中。

    DRIVER CIRCUIT WITH FEED-FORWARD EQUALIZER
    5.
    发明申请
    DRIVER CIRCUIT WITH FEED-FORWARD EQUALIZER 有权
    带前馈均衡器的驱动电路

    公开(公告)号：US20160204768A1

    公开(公告)日：2016-07-14

    申请号：US14825149

    申请日：2015-08-12

    申请人： Mediatek Inc.

    发明人： Yan-Bin Luo ,  Chien-Hua Wu ,  Chung-Shi Lin ,  Chih-Hsien Lin

    IPC分类号： H03K3/012 ,  H04L25/03

    CPC分类号： H03K3/012 ,  H03K19/017509 ,  H03K19/018528 ,  H03K19/018585 ,  H04L25/03076

    摘要： A driver circuit for receiving input data and generating an output signal to a termination element is provided, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; at least one current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and at least one voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to the second bit.

    摘要翻译： 提供了一种用于接收输入数据并向终端元件产生输出信号的驱动电路，其中输入数据具有第一位和第二位，并且驱动电路包括：一对差分输出端，用于输出输出信号，其中 一对差分输出端子具有第一输出端子和第二输出端子; 耦合到所述一对差分输出端子的至少一个电流模式驱动单元，用于从所述第一输出端子和所述第二输出端子之一输出电流，以及从所述第一输出端子和所述第二输出端子中的另一个接收电流 终端根据第一位; 以及耦合到所述一对差分输出端子的至少一个电压模式驱动单元，用于根据所述第二位向所述第一输出端子和所述第二输出端子提供电压。

    INDUCTOR AND INDUCTOR MODULE
    7.
    发明申请
    INDUCTOR AND INDUCTOR MODULE 审中-公开

    公开(公告)号：US20170148558A1

    公开(公告)日：2017-05-25

    申请号：US15135558

    申请日：2016-04-22

    申请人： MEDIATEK INC.

    发明人： Huan-Sheng Chen ,  Yen-Ju Lu ,  Chung-Shi Lin ,  Chien-Hua Wu ,  Yan-Bin Luo

    IPC分类号： H01F27/28 ,  H01F27/29

    CPC分类号： H01F27/28 ,  H01F27/2804 ,  H01F27/29 ,  H01F38/14

    摘要： An inductor module comprising: a first inductor, comprising a first inductor area; and a second inductor, comprising a second inductor area. A first overlapped area of the first inductor area and a second overlapped area of the second inductor area are overlapped. The second overlapped area comprises at least one first magnetic direction area and at least one second magnetic direction area. A ratio between a size of the first magnetic direction area and a size of the second magnetic direction area is a predetermined ratio such that a coupling effect between the first inductor and the second inductor is lower or equals to a predetermined value.

    DRIVER CIRCUIT FOR SIGNAL TRANSMISSION AND CONTROL METHOD OF DRIVER CIRCUIT
    8.
    发明申请
    DRIVER CIRCUIT FOR SIGNAL TRANSMISSION AND CONTROL METHOD OF DRIVER CIRCUIT 有权
    信号传输驱动电路及驱动电路控制方法

    公开(公告)号：US20160197598A1

    公开(公告)日：2016-07-07

    申请号：US15069880

    申请日：2016-03-14

    申请人： MEDIATEK INC.

    发明人： Chien-Hua Wu ,  Yan-Bin Luo

    IPC分类号： H03K3/012 ,  H04B1/04

    CPC分类号： H04B1/04 ,  H03K19/017545 ,  H03K19/018578 ,  H03K19/018585 ,  H04L25/00 ,  H04L25/0272

    摘要： A driver circuit for receiving a data input and generating an output signal to a termination element according to at least the first data input is provided. The driver circuit includes a first output terminal, a current mode drive unit and a voltage mode drive unit. The current mode drive unit is arranged for selectively outputting a first reference current from the first output terminal to the termination element according to the first data input, and selectively receiving the first reference current through the first output terminal according to the first data input. The voltage mode drive unit is arranged for coupling one of a first reference voltage and a second reference voltage different from the second reference voltage to the first output terminal according to the first data input.

    摘要翻译： 提供一种用于接收数据输入并根据至少第一数据输入向终端元件生成输出信号的驱动电路。 驱动电路包括第一输出端子，电流模式驱动单元和电压模式驱动单元。 电流模式驱动单元被布置成根据第一数据输入从第一输出端子选择性地输出第一参考电流到终端元件，并且根据第一数据输入选择性地接收通过第一输出端子的第一参考电流。 电压模式驱动单元被布置成根据第一数据输入将第二参考电压与第二参考电压不同的第二参考电压中的一个耦合到第一输出端。

    MEMORY CONTROLLER, MEMORY MODULE AND MEMORY SYSTEM
    9.
    发明申请
    MEMORY CONTROLLER, MEMORY MODULE AND MEMORY SYSTEM 审中-公开
    存储器控制器，存储器模块和存储器系统

    公开(公告)号：US20150074346A1

    公开(公告)日：2015-03-12

    申请号：US14324228

    申请日：2014-07-06

    申请人： MEDIATEK INC.

    发明人： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Pin Chen

    IPC分类号： G11C7/10 ,  G11C8/12

    CPC分类号： G11C8/12 ,  G06F12/00 ,  G06F13/1668

    摘要： A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

    摘要翻译： 一种存储器模块，包括：第一引脚，布置成接收第一信号; 布置成接收第二信号的第二引脚; 第一导电路径，其具有耦合到第一引脚的第一端; 至少一个存储器芯片，耦合到所述第一导电路径，用于接收所述第一信号; 预定的电阻器，具有耦合到第一导电路径的第二端的第一端子; 以及第二导电路径，其具有耦合到第二引脚的第一端，用于将第二端子传导到预定电阻器的第二端子; 其中所述第一信号和所述第二信号是同步的并且被配置为差分信号，用于使来自所述至少一个存储器芯片的所选择的存储器芯片被访问。