公开(公告)号：US20150277401A1

公开(公告)日：2015-10-01

申请号：US14225478

申请日：2014-03-26

Applicant: MediaTek Inc.

Inventor： Chih-Hsiang HSIAO ,  Li-Chun TU

IPC: G05B15/02

CPC classification number: G05B15/02 ,  B23K9/095 ,  B23K9/32 ,  B23K11/36

Abstract: A low-power wearable controller and associated control method are provided. The wearable controller includes: a processing unit; a memory unit; a peripheral interface unit including a plurality of peripheral interfaces; and a control module, coupled to the processing unit, the memory unit and the peripheral interface unit, wherein the control module is enabled when the wearable controller is operated in a first operation mode, and the control module is disabled when the wearable controller is operated in a second operation mode.

Abstract translation: 提供了一种低功率耐磨控制器和相关控制方法。 可穿戴式控制器包括：处理单元; 记忆单元 包括多个外围接口的外围接口单元; 以及耦合到所述处理单元，所述存储器单元和所述外围接口单元的控制模块，其中当所述可穿戴控制器在第一操作模式下操作时，所述控制模块被启用，并且当所述可穿戴控制器被操作时，所述控制模块被禁用 在第二操作模式中。

公开(公告)号：US20170068304A1

公开(公告)日：2017-03-09

申请号：US14848872

申请日：2015-09-09

Applicant: MediaTek Inc.

Inventor： Yen-Lin LEE ,  Yun-Ching LI ,  Chih-Hsiang HSIAO ,  Yu-Cheng HSIEH ,  Li-Chun TU

IPC: G06F1/32 ,  G06F12/10 ,  G06F3/06 ,  G06F12/06 ,  G06F12/02 ,  G11C14/00 ,  G06F13/28

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G06F12/0238 ,  G06F12/0638 ,  G06F12/0804 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/205 ,  G06F2212/656 ,  G11C14/0036 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: A low-power memory access method and associated apparatus are provided. The apparatus includes a memory controller and a processing unit. The memory controller is coupled to a first memory and a second memory, and includes: a memory management circuit, for allocating physical memory addresses of the first memory and the second memory and controlling access of the first memory and the second memory; and a direct-memory-access (DMA) controller. The processing unit is for accessing the first memory and the second memory via the memory controller. When the apparatus is in an active mode, the memory management circuit copies a portion of data stored in the second memory to the first memory for use by the processing unit, and records dirty data information when the portion of data in the first memory differs from that in the second memory.

Abstract translation: 提供了一种低功率存储器存取方法和相关装置。 该装置包括存储器控制器和处理单元。 存储器控制器耦合到第一存储器和第二存储器，并且包括：存储器管理电路，用于分配第一存储器和第二存储器的物理存储器地址并控制第一存储器和第二存储器的存取; 和直接存储器访问（DMA）控制器。 处理单元用于经由存储器控制器访问第一存储器和第二存储器。 当设备处于活动模式时，存储器管理电路将存储在第二存储器中的数据的一部分复制到第一存储器供处理单元使用，并且当第一存储器中的数据部分不同时记录脏数据信息 在第二个记忆中。

公开(公告)号：US20140189415A1

公开(公告)日：2014-07-03

申请号：US14139951

申请日：2013-12-24

Applicant: MediaTek Inc.

Inventor： Tsung-Huang CHEN ,  Li-Chun TU ,  Wen-Chi CHAO

IPC: G06F1/08

CPC classification number: G06F1/08 ,  G06F13/423

Abstract: A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured.

Abstract translation: 用于处理器和外围设备之间的通信的媒体外围接口包括时钟端口，多个数据I / O和数据选通端口。 时钟端口用于将时钟信号传送到外围设备。 数据I / O被提供用于命令传送到外围设备，以及用于数据传送到外围设备。 数据选通端口用于根据处理器向外围设备发出的指令将数据选通信号传送到外围设备或从外围设备传送数据选通信号。 根据时钟信号，捕获通过数据I / O传送的命令信息。 根据数据选通信号的上升沿和下降沿，捕获通过数据I / O传输的数据。