公开(公告)号：US20240128208A1

公开(公告)日：2024-04-18

申请号：US18471670

申请日：2023-09-21

申请人： ND-HI TECHNOLOGIES LAB, INC. ,  ETRON TECHNOLOGY, INC.

发明人： HO-MING TONG ,  CHAO-CHUN LU

IPC分类号： H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L24/02 ,  H01L21/6835 ,  H01L23/5387 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L24/96 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/73217 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551

摘要： A semiconductor package includes a first integrated circuit (IC) structure. The first IC structure includes: a first body having a first primary surface and a first secondary surface, the first primary surface being substantially perpendicular to the first secondary surface; and an interconnect structure. The interconnect structure includes a primary redistribution layer (RDL) over the first primary surface, the primary RDL having a second secondary surface that is aligned with the first secondary surface of the first body, wherein the first secondary surface and the second secondary surface jointly form a secondary plane. The primary RDL further comprises a first conductive element exposed through the second secondary surface of the primary RDL; and a secondary RDL over the secondary plane, wherein the secondary RDL is electrically connected to the first conductive element of the primary RDL and other conductive elements of the first body exposed through the first secondary plane.

公开(公告)号：US11916035B2

公开(公告)日：2024-02-27

申请号：US17392274

申请日：2021-08-03

申请人： Powertech Technology Inc.

发明人： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L24/73 ,  H01L24/19 ,  H01L24/20 ,  H01L24/26 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L23/481 ,  H01L24/16 ,  H01L24/24 ,  H01L24/32 ,  H01L2224/16145 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24146 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217

摘要： A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.

公开(公告)号：US11881437B2

公开(公告)日：2024-01-23

申请号：US17511787

申请日：2021-10-27

申请人： Infineon Technologies AG

发明人： Eung San Cho

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L25/07 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L23/3135 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L25/072 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24137 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091

摘要： A semiconductor package includes a package substrate that includes an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer, a first semiconductor die that includes a first load terminal disposed on a first surface of the first semiconductor die and a second load terminal disposed on a second surface of the first semiconductor die that is opposite from the first surface of the first semiconductor die, and a liner of dielectric material on the first semiconductor die, wherein the first semiconductor die is embedded within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.

公开(公告)号：US20230387061A1

公开(公告)日：2023-11-30

申请号：US18446554

申请日：2023-08-09

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Wei-Yu CHEN ,  Chi-Yang YU ,  Kuan-Lin HO ,  Chin-Liang CHEN ,  Yu-Min LIANG ,  Jiun Yi WU

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L24/20 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L24/14 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/1431 ,  H01L2924/1437

摘要： A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

公开(公告)号：US11742564B2

公开(公告)日：2023-08-29

申请号：US17321914

申请日：2021-05-17

申请人： MediaTek Inc.

发明人： Nai-Wei Liu ,  Yen-Yao Chi ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC分类号： H01Q1/22 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01Q1/38 ,  H01Q9/16

CPC分类号： H01Q1/2283 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/20 ,  H01Q1/38 ,  H01Q9/16 ,  H01L2223/6677 ,  H01L2224/211 ,  H01L2224/221

摘要： A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.

公开(公告)号：US11721597B2

公开(公告)日：2023-08-08

申请号：US17461479

申请日：2021-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yang-Che Chen ,  Chen-Hua Lin ,  Victor Chiang Liang ,  Huang-Wen Tseng ,  Chwen-Ming Liu

IPC分类号： H01L21/66 ,  H01L23/40 ,  H01L23/58 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L22/32 ,  H01L22/14 ,  H01L23/4006 ,  H01L23/585 ,  H01L24/20 ,  H01L24/13 ,  H01L25/0655 ,  H01L2224/13024 ,  H01L2224/221 ,  H01L2224/2205

摘要： A semiconductor device and a method for detecting a defect in a semiconductor device are provided. The semiconductor device includes a packaging structure. The packaging structure includes a redistribution layer and a detecting component disposed in the redistribution layer. The semiconductor device further includes a cooling plate over the packaging structure and a fixing component penetrating through the packaging structure and the cooling plate. The packaging structure and the cooling plate are fixed by the fixing component. The detecting component is in a chain configuration having a ring shaped structure circling around the fixing component.

公开(公告)号：US20190081023A1

公开(公告)日：2019-03-14

申请号：US16189513

申请日：2018-11-13

申请人： Intel Corporation

发明人： John Guzek

IPC分类号： H01L25/065 ,  H01L25/16 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/221 ,  H01L2224/821 ,  H01L2224/8234 ,  H01L2224/8236 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

公开(公告)号：US20180308815A1

公开(公告)日：2018-10-25

申请号：US16025267

申请日：2018-07-02

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Dae Jung Byun ,  Byung Ho Kim ,  Pyung Hwa Han ,  Joo Young Choi ,  Ung Hui Shin

IPC分类号： H01L23/00 ,  H01L23/28 ,  H01L23/522

CPC分类号： H01L24/09 ,  H01L23/28 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/18 ,  H01L2224/20 ,  H01L2224/221 ,  H01L2224/24155 ,  H01L2224/244 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014

摘要： A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip. The first interconnection member includes a first insulating layer in contact with the second interconnection member, a first redistribution layer disposed on a surface of the first insulating layer in contact with the second interconnection member and electrically connected to the connection pads, and a blocking layer disposed on the surface of the first insulating layer on which the first redistribution layer is disposed and surrounding the through-hole.

公开(公告)号：US20180261571A1

公开(公告)日：2018-09-13

申请号：US15911868

申请日：2018-03-05

申请人： Invensas Corporation

发明人： Belgacem Haba ,  Kyong-Mo Bang

IPC分类号： H01L25/065 ,  B81C1/00 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L25/0655 ,  B81C1/00301 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/367 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/48 ,  H01L24/49 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/221 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package overlying the first microelectronic package and having terminals joined to the stack terminals of the first microelectronic package.

公开(公告)号：US10061967B2

公开(公告)日：2018-08-28

申请号：US15663304

申请日：2017-07-28

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Yong Ho Baek ,  Jung Hyun Cho ,  Byoung Chan Kim

IPC分类号： H05K1/18 ,  G06K9/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC分类号： G06K9/00053 ,  G06K9/0002 ,  H01L21/561 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16238 ,  H01L2224/18 ,  H01L2224/20 ,  H01L2224/221 ,  H01L2224/24155 ,  H01L2224/244 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2924/15153

摘要： A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include first redistribution layers and second redistribution layers electrically connected to the connection pads and formed of one or more layers, at least one of the first redistribution layers is disposed between a plurality of insulating layers of the first connection member, and at least one of the second redistribution layers includes sensor patterns recognizing a fingerprint.