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    Clock and data recovery circuit using an injection locked oscillator
    1.
    发明申请
    Clock and data recovery circuit using an injection locked oscillator 有权
    时钟和数据恢复电路采用注入锁定振荡器

    公开(公告)号：US20150270943A1

    公开(公告)日：2015-09-24

    申请号：US14658256

    申请日：2015-03-16

    Applicant: Mediatek Inc.

    Inventor： Shiue-Shin Liu ,  Chih-Chien Hung ,  Shao-Hung Lin

    IPC: H04L7/00

    CPC classification number: H04L7/0276 ,  H03L7/0995 ,  H03L7/24 ,  H04L7/0037

    Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.

    Abstract translation: 时钟和数据恢复电路包括采样器，偏斜补偿块，脉冲发生器和注入锁定振荡器。 注入锁定振荡器产生恢复的时钟信号，脉冲发生器根据用于控制注入锁定振荡器的输入数据生成脉冲信号，偏斜补偿块补偿输入数据并生成补偿数据，采样器根据 恢复的时钟信号。

    MEMORY CONTROLLER, MEMORY MODULE AND MEMORY SYSTEM
    2.
    发明申请
    MEMORY CONTROLLER, MEMORY MODULE AND MEMORY SYSTEM 审中-公开
    存储器控制器，存储器模块和存储器系统

    公开(公告)号：US20150074346A1

    公开(公告)日：2015-03-12

    申请号：US14324228

    申请日：2014-07-06

    Applicant: MEDIATEK INC.

    Inventor： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Pin Chen

    IPC: G11C7/10 ,  G11C8/12

    CPC classification number: G11C8/12 ,  G06F12/00 ,  G06F13/1668

    Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

    Abstract translation: 一种存储器模块，包括：第一引脚，布置成接收第一信号; 布置成接收第二信号的第二引脚; 第一导电路径，其具有耦合到第一引脚的第一端; 至少一个存储器芯片，耦合到所述第一导电路径，用于接收所述第一信号; 预定的电阻器，具有耦合到第一导电路径的第二端的第一端子; 以及第二导电路径，其具有耦合到第二引脚的第一端，用于将第二端子传导到预定电阻器的第二端子; 其中所述第一信号和所述第二信号是同步的并且被配置为差分信号，用于使来自所述至少一个存储器芯片的所选择的存储器芯片被访问。

    REGULATOR AND REGULATING METHOD
    4.
    发明申请
    REGULATOR AND REGULATING METHOD 有权
    调节器和调节方法

    公开(公告)号：US20150091540A1

    公开(公告)日：2015-04-02

    申请号：US14043859

    申请日：2013-10-02

    Applicant: MEDIATEK INC.

    Inventor： Yan-Bin Luo ,  Chih-Chien Hung

    IPC: G05F1/59

    CPC classification number: G05F1/59 ,  G05F1/46 ,  G05F1/56

    Abstract: A regulator applied to regulate a first reference voltage on an output terminal, the regulator includes: a sensing circuit, arranged to sense a variation of the first reference voltage on the output terminal to generate a sensing signal; and a gain stage, arranged to provide an adjusting current to the output terminal in response to the sensing signal for reducing the variation of the first reference voltage, and the gain stage is coupled in parallel to a loading circuit powered by the first reference voltage.

    Abstract translation: 一种调节器，用于调节输出端子上的第一参考电压，所述调节器包括：感测电路，被布置成感测所述输出端上的所述第一参考电压的变化以产生感测信号; 以及增益级，被布置为响应于用于减小第一参考电压的变化的感测信号向输出端提供调节电流，并且增益级与由第一参考电压供电的负载电路并联耦合。

    Memory controller, memory module and memory system
    5.
    发明授权
    Memory controller, memory module and memory system 有权

    公开(公告)号：US10083728B2

    公开(公告)日：2018-09-25

    申请号：US14324228

    申请日：2014-07-06

    Applicant: MEDIATEK INC.

    Inventor： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Pin Chen

    IPC: G06F12/00 ,  G11C8/12 ,  G06F13/16

    CPC classification number: G11C8/12 ,  G06F12/00 ,  G06F13/1668

    Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

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