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1.发明申请FREQUENCY DIVIDER, CLOCK GENERATING APPARATUS, AND METHOD CAPABLE OF CALIBRATING FREQUENCY DRIFT OF OSCILLATOR 有权频率分频器，时钟发生装置和可校准振荡器频率干扰的方法公开(公告)号：US20140111257A1
公开(公告)日：2014-04-24
申请号：US14048035
申请日：2013-10-07
Applicant: MEDIATEK INC.
Inventor： Yu-Ming Ying , Shiue-Shin Liu
IPC: H03K3/013
CPC classification number: H03K3/013 , H03K7/06 , H03L1/022 , H03L7/1974 , H03L7/1976
Abstract: A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus.
Abstract translation: 时钟发生装置包括振荡器和频率合成器。 振荡器用于产生参考时钟信号。 频率合成器耦合到振荡器，用于根据参考时钟信号和调整或补偿的分频因子来合成目标时钟信号，并输出目标时钟信号作为时钟发生装置的输出。
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公开(公告)号：US09692395B2
公开(公告)日：2017-06-27
申请号：US15067141
申请日：2016-03-10
Applicant: MEDIATEK INC.
Inventor： Yu-Ming Ying , Shiue-Shin Liu
CPC classification number: H03K3/013 , H03K7/06 , H03L1/022 , H03L7/1974 , H03L7/1976
Abstract: A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus.
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3.发明申请FREQUENCY DIVIDER, CLOCK GENERATING APPARATUS, AND METHOD CAPABLE OF CALIBRATING FREQUENCY DRIFT OF OSCILLATOR 有权频率分频器，时钟发生装置和可校准振荡器频率干扰的方法公开(公告)号：US20160197599A1
公开(公告)日：2016-07-07
申请号：US15067141
申请日：2016-03-10
Applicant: MEDIATEK INC.
Inventor： Yu-Ming Ying , Shiue-Shin Liu
CPC classification number: H03K3/013 , H03K7/06 , H03L1/022 , H03L7/1974 , H03L7/1976
Abstract: A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus.
Abstract translation: 时钟发生装置包括振荡器和频率合成器。 振荡器用于产生参考时钟信号。 频率合成器耦合到振荡器，用于根据参考时钟信号和调整或补偿的分频因子来合成目标时钟信号，并输出目标时钟信号作为时钟发生装置的输出。
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4.发明申请OSCILLATING SIGNAL GENERATOR, PHASE-LOCK LOOP CIRCUIT USING THE OSCILLATING SIGNAL GENERATOR AND CONTROL METHOD OF THE OSCILLATING SIGNAL GENERATOR 有权振荡信号发生器，使用振荡信号发生器的相位锁相环电路和振荡信号发生器的控制方法公开(公告)号：US20150280723A1
公开(公告)日：2015-10-01
申请号：US14224078
申请日：2014-03-25
Applicant: MEDIATEK INC.
Inventor： Chi-Wei Fan , Shiue-Shin Liu
CPC classification number: H03L7/099 , H03L7/085 , H03L7/10 , H03L2207/06
Abstract: An oscillating signal generator includes: a controllable oscillator arranged to output an oscillating signal according to a control signal and a band adjusting signal; a control circuit arranged to generate a continuous signal having a specific slew-rate when the control signal reaches a boundary of a control signal interval; and a current mirror arranged to generate the band adjusting signal according to at least the continuous signal.
Abstract translation: 振荡信号发生器包括：可控振荡器，被配置为根据控制信号和频带调整信号输出振荡信号; 控制电路，其被配置为当所述控制信号到达控制信号间隔的边界时产生具有特定转换速率的连续信号; 以及电流镜，布置成根据至少连续信号产生频带调整信号。
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公开(公告)号：US09525543B2
公开(公告)日：2016-12-20
申请号：US15218072
申请日：2016-07-24
Applicant: MEDIATEK INC.
Inventor： Shiue-Shin Liu , Chih-Chien Hung , Shao-Hung Lin
CPC classification number: H04L7/0276 , H03L7/0995 , H03L7/24 , H04L7/0037
Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.
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Patent Agency Ranking
公开(公告)号：US20160337117A1
公开(公告)日：2016-11-17
申请号：US15218072
申请日：2016-07-24
Applicant: MEDIATEK INC.
Inventor： Shiue-Shin Liu , Chih-Chien Hung , Shao-Hung Lin
CPC classification number: H04L7/0276 , H03L7/0995 , H03L7/24 , H04L7/0037
Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.
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公开(公告)号：US09432178B2
公开(公告)日：2016-08-30
申请号：US14658256
申请日：2015-03-16
Applicant: MEDIATEK INC.
Inventor： Shiue-Shin Liu , Chih-Chien Hung , Shao-Hung Lin
CPC classification number: H04L7/0276 , H03L7/0995 , H03L7/24 , H04L7/0037
Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.
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8.发明授权Frequency divider, clock generating apparatus, and method capable of calibrating frequency drift of oscillator 有权分频器，时钟发生装置和能够校准振荡器频率漂移的方法公开(公告)号：US09344065B2
公开(公告)日：2016-05-17
申请号：US14048035
申请日：2013-10-07
Applicant: MEDIATEK INC.
Inventor： Yu-Ming Ying , Shiue-Shin Liu
CPC classification number: H03K3/013 , H03K7/06 , H03L1/022 , H03L7/1974 , H03L7/1976
Abstract: A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus.
Abstract translation: 时钟发生装置包括振荡器和频率合成器。 振荡器用于产生参考时钟信号。 频率合成器耦合到振荡器，用于根据参考时钟信号和调整或补偿的分频因子来合成目标时钟信号，并输出目标时钟信号作为时钟发生装置的输出。
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9.发明授权Oscillating signal generator, phase-lock loop circuit using the oscillating signal generator and control method of the oscillating signal generator 有权振荡信号发生器，使用振荡信号发生器的锁相环电路和振荡信号发生器的控制方法公开(公告)号：US09374099B2
公开(公告)日：2016-06-21
申请号：US14224078
申请日：2014-03-25
Applicant: MEDIATEK INC.
Inventor： Chi-Wei Fan , Shiue-Shin Liu
CPC classification number: H03L7/099 , H03L7/085 , H03L7/10 , H03L2207/06
Abstract: An oscillating signal generator includes: a controllable oscillator arranged to output an oscillating signal according to a control signal and a band adjusting signal; a control circuit arranged to generate a continuous signal having a specific slew-rate when the control signal reaches a boundary of a control signal interval; and a current mirror arranged to generate the band adjusting signal according to at least the continuous signal.
Abstract translation: 振荡信号发生器包括：可控振荡器，被配置为根据控制信号和频带调整信号输出振荡信号; 控制电路，其被配置为当所述控制信号到达控制信号间隔的边界时产生具有特定转换速率的连续信号; 以及电流镜，布置成根据至少连续信号产生频带调整信号。
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公开(公告)号：US20150270943A1
公开(公告)日：2015-09-24
申请号：US14658256
申请日：2015-03-16
Applicant: Mediatek Inc.
Inventor： Shiue-Shin Liu , Chih-Chien Hung , Shao-Hung Lin
IPC: H04L7/00
CPC classification number: H04L7/0276 , H03L7/0995 , H03L7/24 , H04L7/0037
Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.
Abstract translation: 时钟和数据恢复电路包括采样器，偏斜补偿块，脉冲发生器和注入锁定振荡器。 注入锁定振荡器产生恢复的时钟信号，脉冲发生器根据用于控制注入锁定振荡器的输入数据生成脉冲信号，偏斜补偿块补偿输入数据并生成补偿数据，采样器根据 恢复的时钟信号。
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