公开(公告)号：US10887238B2

公开(公告)日：2021-01-05

申请号：US16519112

申请日：2019-07-23

Applicant: Mellanox Technologies Ltd.

Inventor： Carl G. Ramey ,  Matthew Mattina

IPC: H04L12/803 ,  G06F15/173 ,  H04L29/08 ,  H04L12/933

Abstract: A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.

公开(公告)号：US20200177510A1

公开(公告)日：2020-06-04

申请号：US16519112

申请日：2019-07-23

Applicant: Mellanox Technologies Ltd.

Inventor： Carl G. Ramey ,  Matthew Mattina

IPC: H04L12/803 ,  H04L29/08 ,  G06F15/173

Abstract: A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.

公开(公告)号：US10606750B1

公开(公告)日：2020-03-31

申请号：US15484409

申请日：2017-04-11

Applicant: Mellanox Technologies Ltd.

Inventor： Matthew Mattina ,  Chyi-Chang Miao

IPC: G06F12/00 ,  G06F12/0808 ,  G06F12/0811 ,  G06F13/40 ,  G06F12/122 ,  G06F12/128

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

公开(公告)号：US10579524B1

公开(公告)日：2020-03-03

申请号：US15484317

申请日：2017-04-11

Applicant: Mellanox Technologies Ltd.

Inventor： Matthew Mattina ,  Chyi-Chang Miao

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0864

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

公开(公告)号：US11151033B1

公开(公告)日：2021-10-19

申请号：US14208405

申请日：2014-03-13

Applicant: Mellanox Technologies Ltd.

Inventor： David M. Wentzlaff ,  Matthew Mattina ,  Anant Agarwal

IPC: G06F12/08 ,  G06F12/0806 ,  G06F12/084 ,  G06F12/0815 ,  G06F12/0811 ,  G06F12/0897

Abstract: A processor includes a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is associated with information indicating whether data stored in the cache memory is shared among multiple processor cores.

公开(公告)号：US10515045B1

公开(公告)日：2019-12-24

申请号：US15689214

申请日：2017-08-29

Applicant: Mellanox Technologies Ltd.

Inventor： Matthew Mattina

IPC: G06F13/42 ,  G06F13/40

Abstract: A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.

公开(公告)号：US10367741B1

公开(公告)日：2019-07-30

申请号：US15244171

申请日：2016-08-23

Applicant: Mellanox Technologies, Ltd.

Inventor： Carl G. Ramey ,  Matthew Mattina

IPC: H04L12/803 ,  H04L29/08

Abstract: A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.