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公开(公告)号：US10305772B2
公开(公告)日：2019-05-28
申请号：US15077945
申请日：2016-03-23
Applicant: Mellanox Technologies Ltd.
Inventor： Itay Zur , Noam Bloch , Ariel Shahar , Dotan Finkelstein
IPC: H04L12/26 , H04L12/861 , H04L29/08
Abstract: A method for communication includes receiving multiple work requests from a process running on a computer to transmit respective messages over a network. A single work item corresponding to the multiple work requests is submitted to a network interface controller (NIC) connected to the computer. In response to the single work item, multiple data packets carrying the respective messages are transmitted from the NIC to the network.
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Patent Agency Ranking
公开(公告)号：US11599703B2
公开(公告)日：2023-03-07
申请号：US16783237
申请日：2020-02-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Dotan Finkelstein , Roman Manevich , Lidiya Ivanitskaya
IPC: G06F30/398 , G06F21/72 , G06F119/02
Abstract: An apparatus reads a chip design comprising first and second blocks corresponding to first and second hardware modules, nodes, and data path segments that each connect a pair of nodes or a node to a block. Tracing backward along data paths that terminate at the second block, the apparatus identifies a secure cone. The secure cone comprises secure path segments of the data paths terminating at the second block and corresponding nodes. The apparatus identifies data paths originating at the first block and that are at least partially within the secure cone and determines whether any terminate outside the secure cone. When none of the data paths originating at the first block terminate outside the secure cone, the apparatus verifies the chip design. When a data path originating at the first block terminates outside the secure cone, the apparatus determines that the chip design has a potential leak.
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公开(公告)号：US20210248274A1
公开(公告)日：2021-08-12
申请号：US16783237
申请日：2020-02-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Dotan Finkelstein , Roman Manevich , Lidiya Ivanitskaya
IPC: G06F21/72 , G06F30/398
Abstract: An apparatus reads a chip design comprising first and second blocks corresponding to first and second hardware modules, nodes, and data path segments that each connect a pair of nodes or a node to a block. Tracing backward along data paths that terminate at the second block, the apparatus identifies a secure cone. The secure cone comprises secure path segments of the data paths terminating at the second block and corresponding nodes. The apparatus identifies data paths originating at the first block and that are at least partially within the secure cone and determines whether any terminate outside the secure cone. When none of the data paths originating at the first block terminate outside the secure cone, the apparatus verifies the chip design. When a data path originating at the first block terminates outside the secure cone, the apparatus determines that the chip design has a potential leak.
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公开(公告)号：US10572400B2
公开(公告)日：2020-02-25
申请号：US15623426
申请日：2017-06-15
Applicant: Mellanox Technologies, Ltd.
Inventor： Dotan Finkelstein , Lior Narkis , Dror Bohrer , Roee Moyal
IPC: G06F13/16 , G06F13/36 , H04L12/801
Abstract: A packet processing device CPU, including multiple processing cores. A NIC, which is coupled to the CPU, includes at least one network port, receives a flow of incoming data packets in a sequential order from a packet communication network, and receive logic, which delivers the incoming data packets in the flow to a designated group of the cores for processing by the cores in the group, while distributing the incoming data packets to the cores in alternation among the cores in the group. In response to the incoming data packets, the cores in the group generate corresponding outgoing data packets and queue the outgoing data packets for transmission by the NIC in the sequential order of the incoming data packets. Transmit logic in the NIC transmits the outgoing data packets to the network in the sequential order via the at least one network port.
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公开(公告)号：US20180365176A1
公开(公告)日：2018-12-20
申请号：US15623426
申请日：2017-06-15
Applicant: Mellanox Technologies, Ltd.
Inventor： Dotan Finkelstein , Lior Narkis , Dror Bohrer , Roee Moyal
IPC: G06F13/16 , H04L12/801 , G06F13/36
CPC classification number: G06F13/1642 , G06F13/36 , H04L47/34
Abstract: A packet processing device CPU, including multiple processing cores. A NIC, which is coupled to the CPU, includes at least one network port, receives a flow of incoming data packets in a sequential order from a packet communication network, and receive logic, which delivers the incoming data packets in the flow to a designated group of the cores for processing by the cores in the group, while distributing the incoming data packets to the cores in alternation among the cores in the group. In response to the incoming data packets, the cores in the group generate corresponding outgoing data packets and queue the outgoing data packets for transmission by the NIC in the sequential order of the incoming data packets. Transmit logic in the NIC transmits the outgoing data packets to the network in the sequential order via the at least one network port.
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公开(公告)号：US20160294926A1
公开(公告)日：2016-10-06
申请号：US15077945
申请日：2016-03-23
Applicant: Mellanox Technologies Ltd.
Inventor： Itay Zur , Noam Bloch , Ariel Shahar , Dotan Finkelstein
Abstract: A method for communication includes receiving multiple work requests from a process running on a computer to transmit respective messages over a network. A single work item corresponding to the multiple work requests is submitted to a network interface controller (NIC) connected to the computer. In response to the single work item, multiple data packets carrying the respective messages are transmitted from the NIC to the network.
Abstract translation: 一种用于通信的方法包括从计算机上运行的进程接收多个工作请求以通过网络发送相应的消息。 与多个工作请求相对应的单个工作项目被提交给连接到计算机的网络接口控制器（NIC）。 响应于单个工作项，携带相应消息的多个数据分组从NIC传送到网络。
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