公开(公告)号：US07315542B2

公开(公告)日：2008-01-01

申请号：US10261012

申请日：2002-09-30

申请人： Mercedes E Gil ,  S. Paul Tucker ,  Edmundo Rojas

发明人： Mercedes E Gil ,  S. Paul Tucker ,  Edmundo Rojas

IPC分类号： H04L12/28 ,  H04L1/18

CPC分类号： H04L47/10 ,  H04L29/06 ,  H04L47/32 ,  H04L69/22

摘要： A method and structure for the handling and discarding of packets in a packet data network. The method includes a packet data network receiving one or more packets from one or more remote locations and initiating a transfer of a packet of the one or more packets to a remote destination. The remote destination is operable to act as a destination port of a switch. The transfer of the packet is initiated while the packet of the one or more packets is being received, and the packet validity is also checked while the transfer of the packet is initiated. If the packet is invalid, the transfer of the packet of the one or more packets to the remote destination is canceled. Determining packet validity includes inspection of a packet header. The structure has a receive link determining packet validity and passing this error signal to a packet processor. The packet processor has a packet transfer request generator, a packet checker, packet reader, packet memory and tag memory. The packet transfer request generator initiates a transfer request over a switch with a remote destination. While the request is processed, the packet checker verifies packet correctness and stores the packet data for transmission to the remote destination. If a packet is in error, a bad tag is set and the packet transfer is aborted.

摘要翻译： 用于处理和丢弃分组数据网络中的分组的方法和结构。 该方法包括分组数据网络，从一个或多个远程位置接收一个或多个分组，并且发起一个或多个分组的分组到远程目的地的传送。 远程目的地可用作交换机的目的端口。 在接收到一个或多个分组的分组时启动分组的传送，并且在分组的传输被启动时也检查分组有效性。 如果分组无效，则将一个或多个分组的分组传送到远程目的地被取消。 确定包的有效性包括对包头的检查。 该结构具有确定分组有效性的接收链路，并将该错误信号传递给分组处理器。 分组处理器具有分组传输请求生成器，分组检查器，分组读取器，分组存储器和标签存储器。 分组传输请求生成器通过具有远程目的地的交换机发起传送请求。 当请求被处理时，分组检查器验证分组的正确性并存储分组数据以传输到远程目的地。 如果一个数据包出错，则会设置一个错误的标签，并且中继传输数据包。

公开(公告)号：US07313090B2

公开(公告)日：2007-12-25

申请号：US10255788

申请日：2002-09-26

申请人： Edmundo Rojas ,  S. Paul Tucker ,  Mercedes E Gil

发明人： Edmundo Rojas ,  S. Paul Tucker ,  Mercedes E Gil

IPC分类号： H04J1/16

CPC分类号： H04L49/30 ,  H04L47/10 ,  H04L47/39 ,  H04L47/50 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/35

摘要： In general, a system and method for providing data packet flow control is disclosed. Generally, a switch is provided that contains a series of ports, an arbiter and a hub. The arbiter determines an outgoing port, wherein the outgoing port is one port for the series of ports, for transmission of a data packet received by the switch, determines whether the outgoing port is available to receive the received data packet, and regulates transmission of the received data packet to a destination end node. The hub provides a point-to-point connection between any two of the series of ports and the arbiter.

摘要翻译： 通常，公开了一种用于提供数据分组流控制的系统和方法。 通常，提供了包含一系列端口，仲裁器和集线器的交换机。 仲裁器确定出站端口，其中出站端口是一系列端口的一个端口，用于传输交换机接收的数据包，确定出端口是否可用于接收接收到的数据包，并调节 接收到的数据包到目标端节点。 集线器提供了两个系列端口和仲裁器之间的点对点连接。

公开(公告)号：US07209478B2

公开(公告)日：2007-04-24

申请号：US10160938

申请日：2002-05-31

申请人： Edmundo Rojas ,  S. Paul Tucker

发明人： Edmundo Rojas ,  S. Paul Tucker

IPC分类号： H04L12/50

CPC分类号： H04L49/25 ,  H04L49/101 ,  H04L49/201 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/358 ,  H04L49/90

摘要： A switch for use with an InfiniBand network. The switch includes a crossbar that redirects packet-based data based on a forwarding table. At least one port that receives data from a network and selectively transfers that data to the crossbar using a variable number of virtual lanes. A state machine controls the changing of the number of virtual lanes.

摘要翻译： 用于InfiniBand网络的交换机。 交换机包括基于转发表重定向基于分组的数据的交叉开关。 至少一个端口从网络接收数据，并使用可变数量的虚拟通道选择性地将数据传输到交叉开关。 状态机控制虚拟车道数量的变化。

公开(公告)号：US06184902B2

公开(公告)日：2001-02-06

申请号：US08845975

申请日：1997-04-30

申请人： Alan S. Krech, Jr. ,  Theodore G. Rossin ,  Glenn W Strunk ,  Michael S McGrath ,  Edmundo Rojas ,  S Paul Tucker ,  Jon L Ashburn ,  Ted Rakel

发明人： Alan S. Krech, Jr. ,  Theodore G. Rossin ,  Glenn W Strunk ,  Michael S McGrath ,  Edmundo Rojas ,  S Paul Tucker ,  Jon L Ashburn ,  Ted Rakel

IPC分类号： G06F1516

CPC分类号： G06F9/261 ,  G06T1/20

摘要： The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. Finally, a branch central intelligence mechanism controls branching between the control units by defining the next address field.

摘要翻译： 本发明提供一种用于通过提供分支中央智能机构来最小化空间需求并增加用于计算机图形系统的几何加速器的速度的系统和方法。 在结构上，几何加速器包括多个处理元件（例如，算术逻辑单元，乘法器，分频器，比较机构，钳位机构等）和多个控制单元（例如，变换机构， 分解机构，夹子机构，蝴蝶结机构，光机构，分类机构，平面方程机构，雾化机构等），其利用处理元件对图像数据执行数据处理。 根据本发明，控制单元通过微代码实现在只读存储器（ROM）中。 下一个地址字段与每个微代码指令相关联，并定义ROM中要执行的下一条指令的位置。 多个控制单元逻辑元件分别对应控制单元和通过定义下一个地址字段在其各自的控制单元内分支的控制指令。 最后，分支中央智能机构通过定义下一个地址字段来控制控制单元之间的分支。

公开(公告)号：US06219071B1

公开(公告)日：2001-04-17

申请号：US09209934

申请日：1998-10-06

申请人： Alan S. Krech, Jr. ,  Theodore G. Rossin ,  Edmundo Rojas ,  Michael S McGrath ,  Ted Rakel ,  Glenn W Strunk ,  Jon L Ashburn ,  S Paul Tucker

发明人： Alan S. Krech, Jr. ,  Theodore G. Rossin ,  Edmundo Rojas ,  Michael S McGrath ,  Ted Rakel ,  Glenn W Strunk ,  Jon L Ashburn ,  S Paul Tucker

IPC分类号： G06F1516

CPC分类号： G06T1/20

摘要： The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. A branch central intelligence mechanism controls branching between the control units by defining the next address field.

摘要翻译： 本发明提供了一种用于使计算机图形系统的几何加速器中的空间需求最小化并提高速度的系统和方法。 在架构中，系统实现如下。 几何加速器包括多个处理元件（例如，算术逻辑单元，乘法器，分频器，比较机构，钳位机构等）和多个控制单元（例如，变换机构，分解机构 ，夹子机构，蝴蝶结机构，光机构，分类机构，平面方程机构，雾化机构等），其利用处理元件对图像数据进行数据处理。 根据本发明，控制单元通过微代码实现在只读存储器（ROM）中。 下一个地址字段与每个微代码指令相关联，并定义ROM中要执行的下一条指令的位置。 多个控制单元逻辑元件分别对应控制单元和通过定义下一个地址字段在其各自的控制单元内分支的控制指令。 分支中央智能机构通过定义下一个地址字段来控制控制单元之间的分支。

公开(公告)号：US5956047A

公开(公告)日：1999-09-21

申请号：US846363

申请日：1997-04-30

申请人： Alan S. Krech, Jr. ,  Theodore G. Rossin ,  Edmundo Rojas ,  Michael S McGrath ,  Ted Rakel ,  Glenn W Strunk ,  Jon L Ashburn ,  S Paul Tucker

发明人： Alan S. Krech, Jr. ,  Theodore G. Rossin ,  Edmundo Rojas ,  Michael S McGrath ,  Ted Rakel ,  Glenn W Strunk ,  Jon L Ashburn ,  S Paul Tucker

IPC分类号： G06F9/26 ,  G06T1/20 ,  G06T11/00 ,  G06F15/16

CPC分类号： G06T1/20

摘要： The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. A branch central intelligence mechanism controls branching between the control units by defining the next address field.

摘要翻译： 本发明提供了一种用于使计算机图形系统的几何加速器中的空间要求最小化并提高速度的系统和方法。 在架构中，系统实现如下。 几何加速器包括多个处理元件（例如，算术逻辑单元，乘法器，分频器，比较机构，钳位机构等）和多个控制单元（例如，变换机构，分解机构 ，夹子机构，蝴蝶结机构，光机构，分类机构，平面方程机构，雾化机构等），其利用处理元件对图像数据进行数据处理。 根据本发明，控制单元通过微代码实现在只读存储器（ROM）中。 下一个地址字段与每个微代码指令相关联，并定义ROM中要执行的下一条指令的位置。 多个控制单元逻辑元件分别对应控制单元和通过定义下一个地址字段在其各自的控制单元内分支的控制指令。 分支中央智能机构通过定义下一个地址字段来控制控制单元之间的分支。

公开(公告)号：US6137497A

公开(公告)日：2000-10-24

申请号：US866843

申请日：1997-05-30

申请人： Glenn W. Strunk ,  Edmundo Rojas ,  Theodore G. Rossin

发明人： Glenn W. Strunk ,  Edmundo Rojas ,  Theodore G. Rossin

IPC分类号： G06T15/30

CPC分类号： G06T15/30

摘要： A system and method for performing view clipping and model clipping of graphics primitives in a geometry accelerator of a computer graphics system. The method includes performing view clipping and model clipping of the graphics primitives in homogeneous window coordinates. The geometry accelerator includes a transform machine, a light machine, a clipping machine, and a plane equation machine. The transform machine receives vertex data defining a graphics primitive, in object coordinates, and transforms the vertex data into homogeneous window coordinates. The light machine receives the transformed vertex data from the transform machine and enhances the transformed vertex data by simulating lighting conditions of the graphics primitive. The light machine provides light enhanced transformed vertex data to the clipping machine. The clipping machine receives the light enhanced vertex data from the light machine and determines intersections of edges of the graphics primitive with view clipping planes and with any user specified model clipping planes. The resulting clipped vertex data from the clipping machine is provided to the plane equation machine. The plane equation machine calculates plane equations defining geometries formed by the clipped vertex data and provides the calculated plane equations to the computer graphics system for display.

摘要翻译： 一种用于在计算机图形系统的几何加速器中执行图形基元的视图剪切和模型剪切的系统和方法。 该方法包括在均匀窗口坐标中执行图形基元的视图剪切和模型剪切。 几何加速器包括变换机，光机，裁剪机和平面方程机。 变换机器接收以对象坐标定义图形原语的顶点数据，并将顶点数据转换成均匀的窗口坐标。 光机从变换机接收经变换的顶点数据，并通过模拟图形原语的照明条件来增强变换后的顶点数据。 轻型机器向裁剪机提供光增强的变换顶点数据。 裁剪机从光机接收光增强顶点数据，并确定图形基元的边缘与视图剪切平面以及任何用户指定的模型剪切平面的交点。 将来自裁剪机的剪切顶点数据提供给平面方程机。 平面方程机器计算定义由剪切顶点数据形成的几何的平面方程，并将计算出的平面方程提供给计算机图形系统进行显示。

公开(公告)号：US07082504B2

公开(公告)日：2006-07-25

申请号：US10199184

申请日：2002-07-19

申请人： Edmundo Rojas ,  Hui-Sian Ong ,  Robert H Miller, Jr.

发明人： Edmundo Rojas ,  Hui-Sian Ong ,  Robert H Miller, Jr.

IPC分类号： G06F12/00

CPC分类号： G06F5/12 ,  G06F2205/106 ,  G06F2205/123

摘要： A method and apparatus for operating a memory is presented. Information is stored in the memory based on a first time domain and information is read from the memory based on a second time domain. A cooperative relationship is maintained between a write pointer which points to memory locations, where data will be stored and a read pointer which points to memory locations, from which data will be read. A FIFO memory is presented which has memory locations and a register array is presented which stores a bit array that has bit locations. Each bit location in the bit array corresponds to a memory location in the memory. As the write pointer points to a memory location and data is stored in the memory location, a bit (e.g. flag) is set in the bit array. The Flag designates whether the data stored in the memory location is available for reading. Prior to reading information from the memory location, a test is made of the bit location that corresponds to the memory location. The bit value denotes whether the data stored in the memory location is valid data and available for reading.

摘要翻译： 提出了一种用于操作存储器的方法和装置。 基于第一时域将信息存储在存储器中，并且基于第二时域从存储器读取信息。 在指向要存储数据的存储器位置的写指针和指向存储器位置的读指针之间保持协作关系，数据将被读取。 提供了具有存储器位置的FIFO存储器，并且呈现存储具有位位置的位阵列的寄存器阵列。 位阵列中的每个位位置对应于存储器中的存储器位置。 当写指针指向存储器位置并且数据被存储在存储器位置中时，在位阵列中设置位（例如标志）。 该标志指定存储在存储单元中的数据是否可用于读取。 在从存储器位置读取信息之前，测试对应于存储器位置的位位置。 位值表示存储在存储单元中的数据是否为有效数据并可用于读取。

公开(公告)号：US07209476B1

公开(公告)日：2007-04-24

申请号：US09977604

申请日：2001-10-12

申请人： Ian Colloff ,  Norman Chou ,  Richard L. Schober ,  Mercedes Gil ,  Edmundo Rojas ,  Zhang Xiaoyang

发明人： Ian Colloff ,  Norman Chou ,  Richard L. Schober ,  Mercedes Gil ,  Edmundo Rojas ,  Zhang Xiaoyang

IPC分类号： H04L12/50

CPC分类号： H04L49/208 ,  H04L49/101 ,  H04L49/201 ,  H04L49/206

摘要： A networking system includes a plurality of ports, each adapted to send and receive data. A switch core has a first channel configured to receive a logical input flow from each of the plurality of input ports, and has a second channel configured to receive a raw input flow from each of the plurality of input ports. Each logical input flow is carried by its corresponding raw input flow. A plurality of port mirrors are selectable from the plurality of ports. Each of the plurality of port mirrors is configured to produce a duplicate copy of at least one of the logical input flow and the raw input flow available at a selected port.

摘要翻译： 网络系统包括多个端口，每个端口适于发送和接收数据。 交换机核心具有被配置为从多个输入端口中的每一个接收逻辑输入流的第一通道，并且具有被配置为从多个输入端口中的每个输入端口接收原始输入流的第二通道。 每个逻辑输入流由其相应的原始输入流承载。 多个端口镜可以从多个端口中选择。 多个端口反射镜中的每一个被配置为产生在所选端口处可用的逻辑输入流和原始输入流中的至少一个的重复副本。

公开(公告)号：US06990538B2

公开(公告)日：2006-01-24

申请号：US10180675

申请日：2002-06-26

申请人： Edmundo Rojas ,  Hui-Sian Ong

发明人： Edmundo Rojas ,  Hui-Sian Ong

IPC分类号： G06F3/00 ,  H04L1/00 ,  H04L12/28

CPC分类号： H04L49/40 ,  H04L49/358 ,  H04L49/90

摘要： A method and apparatus for managing a communication system including multiple links is presented. A receiver including a First-In, First-out (FIFO) memory receives information communicated on the links. A FIFO is associated with each communication link. Information is written into the FIFO based on a transmitter clock. Information is read out of the FIFO using a receiver clock. The FIFO is used to deskew data communicated across the communication links and re-synchronize the data between the transmitter clock and the receiver clock. A state machine controls the information read out of the FIFO. The state machine includes a deskew enabled state, a deskew disabled state and a reset state. Using the FIFO, the system is able to self reset and transition between the deskew enabled state and the deskew disabled state.

摘要翻译： 提出了一种用于管理包括多个链路的通信系统的方法和设备。 包括先入先出（FIFO）存储器的接收机接收在链路上传送的信息。 FIFO与每个通信链路相关联。 基于发送器时钟将信息写入FIFO。 使用接收机时钟从FIFO读出信息。 FIFO用于在通信链路之间通信的偏移数据，并重新同步发送器时钟和接收机时钟之间的数据。 状态机控制从FIFO读出的信息。 状态机包括启用偏移校正状态，禁用歪斜状态和复位状态。 使用FIFO，系统能够在启用偏移校正的状态和偏移校正禁用状态之间自我复位和转换。