公开(公告)号：US07007060B2

公开(公告)日：2006-02-28

申请号：US10140766

申请日：2002-05-08

申请人： Robert H Miller, Jr.

发明人： Robert H Miller, Jr.

IPC分类号： G06G7/00 ,  G06F1/02

CPC分类号： G06F7/588 ,  H03K3/84

摘要： A method and circuit is presented for generating a random bit stream based on thermal noise of a Complementary Metal Oxide Semiconductor (CMOS) device. A circuit implementing the invention preferably includes at least a pair of identically implemented thermal noise generators whose outputs feed a differential amplifier. The differential amplifier measures and amplifies the difference between the noise signals. A sampling circuit compares the difference with a threshold value that is selected to track with process/voltage/temperature variations of the noise generator circuits to output a binary bit having a bit value determined according to the polarity of the noise difference signal relative to the threshold value. The sampling circuit may be clocked to generate a random bit stream.

摘要翻译： 提出了一种基于互补金属氧化物半导体（CMOS）器件的热噪声产生随机位流的方法和电路。 实施本发明的电路优选地包括至少一对相同实现的热噪声发生器，其输出馈送差分放大器。 差分放大器测量和放大噪声信号之间的差异。 采样电路将该差与阈值进行比较，所述阈值被选择跟随噪声发生器电路的过程/电压/温度变化跟踪，以输出具有根据噪声差信号的极性相对于阈值确定的位值的二进制位 值。 采样电路可以被计时以产生随机比特流。

公开(公告)号：US06576629B1

公开(公告)日：2003-06-10

申请号：US09369298

申请日：1999-08-06

申请人： David Oppong ,  Marilyn S. Whittemore ,  M. Sheldon Ellis ,  Robert H. Miller, Jr. ,  Xiaugdong Zhou ,  Michael E. Elmore

发明人： David Oppong ,  Marilyn S. Whittemore ,  M. Sheldon Ellis ,  Robert H. Miller, Jr. ,  Xiaugdong Zhou ,  Michael E. Elmore

IPC分类号： A61K31535

CPC分类号： A01N43/653 ,  A01N43/84 ,  A01N43/80 ,  A01N43/76 ,  A01N43/50 ,  A01N43/46 ,  A01N43/40 ,  A01N43/36 ,  A01N2300/00

摘要： A method for increasing the effectiveness of the microbicide propiconazole, (RS)-1-2-[(2,4-dichlorophenyl)-2-propyl-1,3-dioxalan-2ylmethyl]-1H-1,2,4-triazole, is described. In the method, propiconazole and a potentiator, an N-alkyl heterocyclic compound, its salt, or a mixture thereof, are applied to a substrate or aqueous system subject to the growth of microorganisms. The N-alkyl heterocyclic compound, its salt, or a mixture thereof is applied in an amount effective to increase the microbicidal activity of the microbicide. The N-alkyl heterocyclic compound has the formula: The variable “n” ranges from 5 to 17, and the heterocyclic ring defined by is a substituted or unsubstituted ring having four to eight members. Microbicidal compositions are described where propiconazole and an N-alkyl heterocyclic compound, its salt, or a mixture thereof are present in a combined amount: effective to control the growth of at least one microorganism. Methods for controlling the growth of microorganisms on various substrates and in various aqueous systems are also described. The combination of propiconazole and an N-alkyl heterocyclic compound, its salt, or a mixture thereof is particularly useful as microbicidal in the leather industry, the lumber industry, the papermaking industry, the textile industry, the agricultural industry, and the coating industry, as well as in industrial process waters.

摘要翻译： 提高杀微生物剂丙环唑（RS）-1-2 - [（2,4-二氯苯基）-2-丙基-1,3-二氧杂环戊烷-2-基甲基] -1H-1,2,4-三唑的有效性的方法 ，被描述。 在该方法中，将丙环唑和增效剂，N-烷基杂环化合物，其盐或其混合物施加到受微生物生长影响的底物或水性体系上。 以有效提高杀微生物剂的杀菌活性的量施用N-烷基杂环化合物，其盐或其混合物。 N-烷基杂环化合物具有下式：变量“n”为5至17，并且由取代或未取代的环具有四至八个成员所定义的杂环。 描述了杀微生物组合物，其中丙环唑和N-烷基杂环化合物，其盐或其混合物以有效控制至少一种微生物生长的组合量存在。 还描述了控制各种底物和各种水性体系中微生物生长的方法。 丙环唑和N-烷基杂环化合物，其盐或其混合物的组合在皮革工业，木材工业，造纸工业，纺织工业，农业和涂料工业中特别可用作杀菌剂， 以及工业过程水域。

公开(公告)号：US5889979A

公开(公告)日：1999-03-30

申请号：US653645

申请日：1996-05-24

申请人： Robert H. Miller, Jr. ,  Samuel D. Naffziger

发明人： Robert H. Miller, Jr. ,  Samuel D. Naffziger

IPC分类号： G06F7/00 ,  G06F9/38 ,  H03K3/356 ,  G06F1/12 ,  G06F13/20

CPC分类号： H03K3/356165 ,  G06F9/3869

摘要： A system and method for transferring data between alternately evaluated first and second logic blocks of a dynamic logic pipeline. Associated with the system and method is a transparent data-triggered pipeline latch for controlling data flow between the first and second logic blocks. During an evaluation period accorded the first logic block, data existing at the logic block's data inputs is evaluated. Substantially simultaneously, the data-triggered latch is reset. As valid data is output from the first logic block, the latch is triggered. Immediately after the latch has been triggered, and before a clock-triggered evaluation period is accorded the second logic block, the data stored in the latch is output to the second logic block. Propagation of the early arriving data may be halted by ANDing the early arriving data signals with clocked signals which remain invalid. The invalid signals may comprise clock or data signals. Early arriving data is beneficial when supplied to static logic gates, or when transmitted through heavily loaded data lines which are associated with a propagation delay. A preferred embodiment of the latch comprises high and low level mousetrap data controls. Each control is coupled with a respective high or low level mousetrap data input, output, and storage node, and further comprises an input trigger, an input trigger disabler, a data storage device, a reset mechanism, and a reset disabler. The latch allows data to be driven out when valid, rather than in response to a clock edge.

摘要翻译： 一种用于在动态逻辑管线的交替评估的第一和第二逻辑块之间传送数据的系统和方法。 与系统和方法相关联的是用于控制第一和第二逻辑块之间的数据流的透明数据触发流水线锁存器。 在给定第一逻辑块的评估期间，评估存在于逻辑块的数据输入端的数据。 基本同时，数据触发锁存器被复位。 当有效数据从第一个逻辑块输出时，锁存器被触发。 在锁存器被触发之后，并且在时钟触发的评估周期被赋予第二逻辑块之前，存储在锁存器中的数据被输出到第二逻辑块。 早期到达数据的传播可以通过将早期到达的数据信号与保持无效的时钟信号进行AND运算而停止。 无效信号可以包括时钟或数据信号。 提供给静态逻辑门，或通过与传播延迟相关联的重载数据线传输时，提前到达的数据是有益的。 锁存器的优选实施例包括高和低电平的捕鼠器数据控制。 每个控制与相应的高或低级捕鼠器数据输入，输出和存储节点耦合，并且还包括输入触发器，输入触发器，数据存储设备，复位机构和复位禁用器。 锁存器允许数据在有效时被驱出，而不是响应于时钟边沿。

公开(公告)号：US5224208A

公开(公告)日：1993-06-29

申请号：US494708

申请日：1990-03-16

申请人： Robert H. Miller, Jr. ,  Roger W. Swanson

发明人： Robert H. Miller, Jr. ,  Roger W. Swanson

IPC分类号： G06T11/20 ,  G06T15/04

CPC分类号： G06T15/04

摘要： A method and apparatus for performing the majority of texture map gradient calculations once per polygon so as to increase processing speed in a graphics system. Texture values are identified for each vertex of an input polygon and are interpolated over the polygon in perspective space in order to find the corresponding values at a given pixel within the polygon. The perspective values of the vertices are linearly interpolated across the polygon to determine the value at the given pixel. The texture gradients are then calculated by defining vectors perpendicular and parallel to the horizon of the plane containing the input polygon so that the resulting components may be calculated. The resulting value is the texture gradient, which may then be used to address a texture map to determine the pre-filtered texture value for that point. A hardware implementation performs the necessary calculations for each pixel in the input polygon. The invention so arranged removes artifacts in the texture mapped image at a low cost and at a high speed.

公开(公告)号：US07196558B2

公开(公告)日：2007-03-27

申请号：US11076758

申请日：2005-03-10

申请人： Robert H Miller, Jr.

发明人： Robert H Miller, Jr.

IPC分类号： H03K21/00

CPC分类号： H03K23/54

摘要： An apparatus has a frequency divider accepting a clock. The frequency divider is selectable between an N divide factor and an M divide factor via a divide mode signal, where an absolute value of (N−M)=1. The apparatus also has a pulse generator responsive to a slip signal and driven by an output of the frequency divider and providing the divide mode signal to the frequency divider.

摘要翻译： 装置具有接收时钟的分频器。 分频器可以通过分频模式信号在N分频因子和M分频因子之间进行选择，其中绝对值（N-M）= 1。 该装置还具有响应于滑差信号并由分频器的输出驱动并将分频模式信号提供给分频器的脉冲发生器。

公开(公告)号：US06549924B1

公开(公告)日：2003-04-15

申请号：US09410409

申请日：1999-10-01

申请人： Robert H Miller, Jr.

发明人： Robert H Miller, Jr.

IPC分类号： G06F102

CPC分类号： G06T3/403

摘要： An input number is applied to a look-up table that supplies three coefficients based upon certain bits of the input that define a series of bins. The first coefficient is fed directly to an adder that produces the output. The second coefficient is multiplied by a number corresponding to how far the input is from the edge of a bin. This number is then input to the adder that produces the output. The third coefficient is multiplied by a number that is the result of a curve-fit function of a number corresponding to how far the input is from the middle of a bin. This result is then input to the adder that produces the output. These three addends are aligned and summed to produce an output that corresponds within a certain precision of a chosen mathematical function of the input such as the mathematical inverse (1/x) or the mathematical inverse of the square root of the input.

摘要翻译： 输入数字被应用于基于定义一系列仓的输入的某些位提供三个系数的查找表。 第一系数被直接馈送到产生输出的加法器。 第二个系数乘以一个对应于输入距离一个仓边的距离多少的数字。 然后将该数字输入到产生输出的加法器。 第三个系数乘以一个数字，该数字是一个数字的曲线拟合函数的结果，该数字对应于输入距离一个仓的中间多远。 然后将该结果输入到产生输出的加法器。 这三个加数对齐并相加以产生在输入的所选数学函数的一定精度内对应的输出，例如数学逆（1 / x）或输入的平方根的数学倒数。

公开(公告)号：US5798952A

公开(公告)日：1998-08-25

申请号：US608798

申请日：1996-02-29

申请人： Robert H. Miller, Jr. ,  Rudolfo G. Beraha

发明人： Robert H. Miller, Jr. ,  Rudolfo G. Beraha

IPC分类号： G06F7/00 ,  G06F7/74 ,  G06F7/38 ,  G06F7/50

CPC分类号： G06F7/74 ,  G06F7/485

摘要： Improved and less complicated leading bit anticipation (LBA) for a PKG floating point adder of n-bit 2's complement operands is accomplished by representing de-normalized (n+1)-bit operands as (n+1)-many PKG symbols. These are grouped into (n-1)-many triples, each of which has two adjacent PKG symbols in common with its neighboring triple. Presuming the existence of a least significant PKG symbol of K allows the formation of an additional triple of lesser significance. Each triple produces an associated transition bit that when set indicates, for the partial summation segment of the raw sum of bit location corresponding to the location of the triple, if the left-most two bits of the corresponding partial summation segment are, or would be with a carry-in, of opposite bit values. The bit position of the most-significant set transition bit is determined in terms of how many bit positions J that is from the most significant transition bit position. The raw sum is normalized by shifting it left by J-many bit positions and adjusting its exponent by J. If J is one too low in value then the raw sum is shifted and its exponent is adjusted by one extra count. When no transition bits are set, the raw sum is zero. A raw sum of zero does not need normalization, although the zero case needs to cause a forced a zero for the exponent. If a slightly different rule is used for determining the transition bit of the MSB, then a simplification of the rule for producing transition bits for all remaining bit positions is possible. That simplification is that any triple whose center symbol is P can produce an associated transition bit of zero.

摘要翻译： 通过将去标准化（n + 1）位操作数表示为（n + 1） - 多个PKG符号来实现n位2的补码操作数的PKG浮点加法器的改进和较不复杂的前导比特预期（LBA）。 它们被分组为（n-1） - 多个三元组，每个三元组具有与其相邻三元组相同的两个相邻的PKG符号。 假设存在K的最不重要的PKG符号，可以形成另外三倍的重要性。 每个三进制产生一个关联的转换位，当被设置指示对于对应于三重位置的位置的位位置的原始和的部分求和段时，如果对应的部分求和段的最左侧的两个位是或将是 带有进位，相对位值。 根据从最重要的转换位位置开始的位数J来确定最重要的转换位的位位置。 原始和通过向左移动J个位位置并将其指数调整为J来进行归一化。如果J值太低，则原始和移位，并且其指数被调整一个额外的计数。 当没有设置转换位时，原始和为零。 零的原始和不需要归一化，尽管零情况需要使指数强制为零。 如果使用稍微不同的规则来确定MSB的转换位，则可以简化用于产生所有剩余位位置的转换位的规则。 这种简化是任何三角形的中心符号是P可以产生一个相关的转换位零。

公开(公告)号：US5740181A

公开(公告)日：1998-04-14

申请号：US662403

申请日：1996-06-12

申请人： Craig A. Heikes ,  Glenn T. Colon-Bonet ,  David R. Smentek ,  Robert H. Miller, Jr.

发明人： Craig A. Heikes ,  Glenn T. Colon-Bonet ,  David R. Smentek ,  Robert H. Miller, Jr.

IPC分类号： G01R31/3185 ,  G06F11/00

CPC分类号： G01R31/318522

摘要： The operation of a pipeline is observed by launching two or more sets of data into the pipeline on consecutive clock cycles. The clock free-runs for as many cycles as it takes the data to propagate through the stages of the pipeline. The output latches of each stage of the pipeline are only sampled when the data of interest is held in each output latch, respectively. Observation may be completely controlled through a standard test access port (TAP). Observation may be accomplished by halting the clock to scan new data in and results out, or with the clock free-running. The inputs to the pipeline may come from test registers or from circuitry which feeds the pipeline during normal operation.

摘要翻译： 通过在连续的时钟周期内将两组或更多组数据发送到流水线来观察流水线的操作。 时钟自由运行，因为它需要数据传播通过管道的阶段。 只有当感兴趣的数据分别保存在每个输出锁存器中时，才会对流水线的每一级的输出锁存器进行采样。 观察可以通过标准测试访问端口（TAP）完全控制。 观察可以通过暂停时钟来扫描新数据并导出，或者与时钟自由运行来实现。 管道的输入可能来自测试寄存器或来自在正常操作期间馈送流水线的电路。

公开(公告)号：US5691652A

公开(公告)日：1997-11-25

申请号：US603977

申请日：1996-02-20

申请人： Robert H. Miller, Jr. ,  John R. Spencer

发明人： Robert H. Miller, Jr. ,  John R. Spencer

IPC分类号： H01L27/04 ,  H01L21/822 ,  H03K3/356 ,  H03K19/00 ,  H03K19/003 ,  H03K19/096 ,  H03K17/16

CPC分类号： H03K19/00338 ,  H03K3/35606

摘要： A system and method for improving alpha-particle induced soft error rates in integrated circuits is provided. Logic isolation circuits implemented using a substantially fewer number of pn-junctions are situated at the outputs of fast logic portions containing a substantially greater number of pn-junctions. The present invention reduces the vulnerability of a dynamic logic circuit of incurring alpha soft errors by effectively trading the probability of an isolation circuit composed of only a few pn-junctions incurring alpha-particle strikes with the probability of a fast logic circuit having substantially more pn-junctions incurring alpha-particle strikes. By reducing the number of pn-junctions susceptible to alpha-particle strikes, the present invention significantly lowers the potential alpha-particle induced soft error rate. In one embodiment, isolation circuits used in the present invention are implemented using self-timed logic, to reduce the window in which a circuit is logically vulnerable to alpha strikes, in which a loss of state can occur.

摘要翻译： 提供了一种用于提高集成电路中α粒子诱导的软错误率的系统和方法。 使用基本上较少数量的pn结实现的逻辑隔离电路位于包含基本上更多数量的pn结的快速逻辑部分的输出处。 本发明通过有效地交换由仅具有几个pn结组成的隔离电路的概率来降低产生阿尔法软错误的动态逻辑电路的脆弱性，其中快速逻辑电路具有基本上更多的pn的概率 - 引起α粒子撞击的结点。 通过减少易受α-粒子撞击的pn结的数量，本发明显着降低了潜在的α粒子诱导的软错误率。 在一个实施例中，本发明中使用的隔离电路使用自定时逻辑来实现，以减少电路逻辑上容易受到可能发生状态损失的α打击的窗口。

公开(公告)号：US5557620A

公开(公告)日：1996-09-17

申请号：US533415

申请日：1995-09-25

申请人： Robert H. Miller, Jr. ,  Craig A. Heikes

发明人： Robert H. Miller, Jr. ,  Craig A. Heikes

IPC分类号： G01R31/26 ,  G01R31/30 ,  G01R31/317 ,  H01L21/66 ,  G06F11/00

CPC分类号： G01R31/3004

摘要： A system and method for quiescent current testing of dynamic logic circuitry. Nodes shorted to ground are detected during a dynamic pre-charge state. Nodes shorted to a power supply potential are detected by driving all nodes of interest to ground during a dynamic evaluation phase. Nodes of interest are driven to ground directly by one additional transistor per node or indirectly by logical propagation from upstream nodes. As a result, only two current measurements are needed for all shorted node faults, even for pipelined systems with multiple clocks. There is no need for input test signal sequences and no need for signal propagation to outputs for detection. Specific embodiments are provided for single-rail logic, single-rail pipelined systems, dual-rail logic and dual-rail pipelined systems. For single-rail pipelined systems, optional transistors between stages enable preservation of logical states during testing. For dual-rail logic, storage nodes and static nodes are forced to a logical state that is not possible during normal operation. For pipelined dual-rail logic, testing of alternate stages inherently preserves the logical state of the system during testing.

摘要翻译： 一种静态电流测试动态逻辑电路的系统和方法。 在动态预充电状态期间检测到接地短路的节点。 通过在动态评估阶段将感兴趣的所有节点驱动到地面来检测短路到电源电位的节点。 感兴趣的节点通过每个节点的一个附加晶体管直接驱动到地，或间接通过来自上游节点的逻辑传播。 因此，即使对于具有多个时钟的流水线系统，所有短路节点故障都只需要两个电流测量。 不需要输入测试信号序列，不​​需要信号传播到输出进行检测。 为单轨逻辑，单轨流水线系统，双轨逻辑和双轨流水线系统提供具体实施例。 对于单轨流水线系统，阶段之间的可选晶体管能够在测试期间保持逻辑状态。 对于双轨逻辑，存储节点和静态节点被强制为在正常操作期间不可能的逻辑状态。 对于流水线双轨逻辑，替代阶段的测试固有地保留系统在测试期间的逻辑状态。