公开(公告)号：US11868281B2

公开(公告)日：2024-01-09

申请号：US17818196

申请日：2022-08-08

Applicant: Meta Platforms Technologies, LLC

Inventor： Alok Kumar Mathur ,  Ennio Salemi ,  Drew Eric Wingard ,  Valerio Catalano

IPC: G06F13/16 ,  G06T19/00 ,  G02B27/01 ,  G06F3/01 ,  G06V20/20

CPC classification number: G06F13/1626 ,  G02B27/0172 ,  G06F3/011 ,  G06F13/161 ,  G06F13/1642 ,  G06T19/006 ,  G06V20/20

Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.

公开(公告)号：US20220391331A1

公开(公告)日：2022-12-08

申请号：US17818196

申请日：2022-08-08

Applicant: Meta Platforms Technologies, LLC

Inventor： Alok Kumar Mathur ,  Ennio Salemi ,  Drew Eric Wingard ,  Valerio Catalano

IPC: G06F13/16 ,  G06T19/00 ,  G02B27/01 ,  G06F3/01 ,  G06V20/20

Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.

公开(公告)号：US20230267078A1

公开(公告)日：2023-08-24

申请号：US18310953

申请日：2023-05-02

Applicant: Meta Platforms Technologies, LLC

Inventor： Sridhar Gurumurthy Isukapalli Sharma ,  Drew Eric Wingard

IPC: G06F12/0864 ,  G06F12/0891 ,  G06F12/02 ,  G06F3/01 ,  G06F15/78

CPC classification number: G06F12/0864 ,  G06F12/0891 ,  G06F12/0246 ,  G06F3/012 ,  G06F15/7807

Abstract: A system and method for accessing cache lines of an N-way set associative cache distributed across local memory of compute elements. The set associative cache includes a plurality of sets, with each location in cacheable local memory mapped to one of the sets and each set including N locations for caching data blocks read from the cacheable memory. Each set is mapped to one of the local memories, when that local memory is not in use by local compute elements. A cache controller is configured to receive a read request, to identify a data block in the cacheable memory associated with the address, to determine if the identified data block is in cache in one of the local memories, and, if the identified data block is in cache in one of the local memories, to fetch the identified data block from the cache.

公开(公告)号：US11474970B2

公开(公告)日：2022-10-18

申请号：US16726492

申请日：2019-12-24

Applicant: Meta Platforms Technologies, LLC

Inventor： Jun Wang ,  Neeraj Upasani ,  Wojciech Stefan Powiertowski ,  Drew Eric Wingard ,  Gregory Edward Ehmann ,  Marco Brambilla ,  Minli Lin ,  Miguel Angel Guerrero

IPC: G06F15/163 ,  H04N13/344 ,  G06F15/173 ,  G06F15/167

Abstract: The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.

公开(公告)号：US11681627B1

公开(公告)日：2023-06-20

申请号：US17504292

申请日：2021-10-18

Applicant: Meta Platforms Technologies, LLC

Inventor： Sridhar Gurumurthy Isukapalli Sharma ,  Drew Eric Wingard

IPC: G06F12/08 ,  G06F12/0864 ,  G06F12/0891 ,  G06F3/01 ,  G06F15/78 ,  G06F12/02

CPC classification number: G06F12/0864 ,  G06F3/012 ,  G06F12/0246 ,  G06F12/0891 ,  G06F15/7807

Abstract: A system and method for accessing cache lines of an N-way set associative cache distributed across local memory of compute elements. The set associative cache includes a plurality of sets, with each location in cacheable local memory mapped to one of the sets and each set including N locations for caching data blocks read from the cacheable memory. Each set is mapped to one of the local memories, when that local memory is not in use by local compute elements. A cache controller is configured to receive a read request, to identify a data block in the cacheable memory associated with the address, to determine if the identified data block is in cache in one of the local memories, and, if the identified data block is in cache in one of the local memories, to fetch the identified data block from the cache.