公开(公告)号：US07378343B2

公开(公告)日：2008-05-27

申请号：US11164285

申请日：2005-11-17

Applicant: Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

Inventor： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

IPC: H01L21/4763

CPC classification number: H01L21/7681 ,  H01L21/76829

Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

Abstract translation: 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

公开(公告)号：US20070125750A1

公开(公告)日：2007-06-07

申请号：US11674678

申请日：2007-02-14

Applicant: Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

Inventor： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

IPC: C23F1/00 ,  H01L21/302 ,  B44C1/22

CPC classification number: H01L21/31144 ,  H01L21/02063 ,  H01L21/76811 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/963

Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues.

Abstract translation: 低k绝缘膜沉积在晶片上。 然后在低k电介质膜上沉积金属层。 在金属层上形成抗蚀剂图案。 然后将抗蚀剂图案转移到下面的金属层以形成金属图案。 剥离抗蚀剂图案。 通过使用金属图案作为硬掩模将通孔等离子体蚀刻到低k电介质膜中。 等离子体蚀刻导致残留物沉积在通孔内。 然后进行湿处理以软化残留物。 进行等离子体干燥处理以破坏残留物。

公开(公告)号：US20070111514A1

公开(公告)日：2007-05-17

申请号：US11164285

申请日：2005-11-17

Applicant: Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

Inventor： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

IPC: H01L21/473

CPC classification number: H01L21/7681 ,  H01L21/76829

Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

Abstract translation: 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

公开(公告)号：US20060252256A1

公开(公告)日：2006-11-09

申请号：US10908374

申请日：2005-05-09

Applicant: Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

Inventor： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/311 ,  H01L21/302

CPC classification number: H01L21/31144 ,  H01L21/02063 ,  H01L21/76811 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/963

Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A first wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues. A second wet treatment is performed to completely remove the residues.

Abstract translation: 低k绝缘膜沉积在晶片上。 然后在低k电介质膜上沉积金属层。 在金属层上形成抗蚀剂图案。 然后将抗蚀剂图案转移到下面的金属层以形成金属图案。 剥离抗蚀剂图案。 通过使用金属图案作为硬掩模将通孔等离子体蚀刻到低k电介质膜中。 等离子体蚀刻导致残留物沉积在通孔内。 然后进行第一次湿处理以软化残留物。 进行等离子体干燥处理以破坏残留物。 进行第二次湿处理以完全去除残留物。

公开(公告)号：US07628866B2

公开(公告)日：2009-12-08

申请号：US11562989

申请日：2006-11-23

Applicant: Miao-Chun Lin ,  Cheng-Ming Weng ,  Chun-Jen Huang

Inventor： Miao-Chun Lin ,  Cheng-Ming Weng ,  Chun-Jen Huang

IPC: B08B3/04

CPC classification number: H01L21/02063 ,  H01L21/76807 ,  H01L21/76814 ,  Y10S134/902 ,  Y10S438/906

Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.

Abstract translation: 提供了在蚀刻处理之后清洁晶片的方法。 提供了具有蚀刻停止层，电介质层，依次形成的图案化金属硬掩模的基板。 使用图案化金属硬掩模，在介电层中限定开口。 开口露出一部分蚀刻停止层。 在氦气的环境中进行干蚀刻处理以除去由开口露出的蚀刻停止层。 使用氮和氢的混合物作为反应气体在晶片表面上进行干洗处理。 使用含有微量氢氟酸的清洗溶液在晶片表面上进行湿式清洗处理。

公开(公告)号：US20080121619A1

公开(公告)日：2008-05-29

申请号：US11562989

申请日：2006-11-23

Applicant: Miao-Chun Lin ,  Cheng-Ming Weng ,  Chun-Jen Huang

Inventor： Miao-Chun Lin ,  Cheng-Ming Weng ,  Chun-Jen Huang

IPC: C23F1/00 ,  B08B3/08 ,  B08B5/00

CPC classification number: H01L21/02063 ,  H01L21/76807 ,  H01L21/76814 ,  Y10S134/902 ,  Y10S438/906

Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.

Abstract translation: 提供了在蚀刻处理之后清洁晶片的方法。 提供了具有蚀刻停止层，电介质层，依次形成的图案化金属硬掩模的基板。 使用图案化金属硬掩模，在介电层中限定开口。 开口露出一部分蚀刻停止层。 在氦气的环境中进行干蚀刻处理以除去由开口露出的蚀刻停止层。 使用氮和氢的混合物作为反应气体在晶片表面上进行干洗处理。 使用含有微量氢氟酸的清洗溶液在晶片表面上进行湿式清洗处理。

公开(公告)号：US07192878B2

公开(公告)日：2007-03-20

申请号：US10908374

申请日：2005-05-09

Applicant: Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

Inventor： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/31144 ,  H01L21/02063 ,  H01L21/76811 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/963

Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A first wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues. A second wet treatment is performed to completely remove the residues.

Abstract translation: 低k绝缘膜沉积在晶片上。 然后在低k电介质膜上沉积金属层。 在金属层上形成抗蚀剂图案。 然后将抗蚀剂图案转移到下面的金属层以形成金属图案。 剥离抗蚀剂图案。 通过使用金属图案作为硬掩模将通孔等离子体蚀刻到低k电介质膜中。 等离子体蚀刻导致残留物沉积在通孔内。 然后进行第一次湿处理以软化残留物。 进行等离子体干燥处理以破坏残留物。 进行第二次湿处理以完全去除残留物。

公开(公告)号：US20070249165A1

公开(公告)日：2007-10-25

申请号：US11399084

申请日：2006-04-05

Applicant: Chun-Jen Huang ,  Cheng-Ming Weng ,  Meng-Jun Wang

Inventor： Chun-Jen Huang ,  Cheng-Ming Weng ,  Meng-Jun Wang

IPC: H01L21/4763

CPC classification number: H01L21/76811

Abstract: A dual damascene process is provided. A substrate having a conductive area is provided. An etching stop layer, a dielectric layer and a patterned hard mask layer are sequentially formed on the substrate. A first opening is formed in the dielectric layer exposed by the patterned hard mask layer. A first material layer having a high etching selectivity with respect to the dielectric layer is deposited to fill the first opening. A portion of the dielectric layer and the filling material layer are removed to form a trench and a second opening. The filling material layer exposed by the second opening is removed to expose part of the etching stop layer. A portion of the etching stop layer is removed to form a third opening. A conductive layer is formed in the trench and the third opening.

Abstract translation: 提供了双镶嵌工艺。 提供具有导电区域的基板。 蚀刻停止层，电介质层和图案化的硬掩模层依次形成在基板上。 在由图案化的硬掩模层暴露的电介质层中形成第一开口。 沉积相对于电介质层具有高蚀刻选择性的第一材料层以填充第一开口。 去除介电层和填充材料层的一部分以形成沟槽和第二开口。 去除由第二开口暴露的填充材料层以暴露部分蚀刻停止层。 去除蚀刻停止层的一部分以形成第三开口。 在沟槽和第三开口中形成导电层。

公开(公告)号：US20130285737A1

公开(公告)日：2013-10-31

申请号：US13460112

申请日：2012-04-30

Applicant: Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

Inventor： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

IPC: G05F3/02

CPC classification number: H02M3/07

Abstract: In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.

Abstract translation: 在一个方面，第一电荷泵具有串联布置的电荷泵级。 相邻级之间的阶段节点由第二电荷泵泵送。 在另一方面，电荷泵级的定时由命令时钟信号控制。 命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。

公开(公告)号：US20080171433A1

公开(公告)日：2008-07-17

申请号：US11621996

申请日：2007-01-11

Applicant: Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

Inventor： Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

IPC: H01L21/768

CPC classification number: H01L21/76811

Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.

Abstract translation: 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF 4 N 3 N 3等离子体从双镶嵌开口选择性地去除暴露的盖层。