公开(公告)号：US07378343B2

公开(公告)日：2008-05-27

申请号：US11164285

申请日：2005-11-17

申请人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

发明人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

IPC分类号： H01L21/4763

CPC分类号： H01L21/7681 ,  H01L21/76829

摘要： A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

摘要翻译： 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

公开(公告)号：US20070125750A1

公开(公告)日：2007-06-07

申请号：US11674678

申请日：2007-02-14

申请人： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

发明人： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

IPC分类号： C23F1/00 ,  H01L21/302 ,  B44C1/22

CPC分类号： H01L21/31144 ,  H01L21/02063 ,  H01L21/76811 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/963

摘要： A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues.

摘要翻译： 低k绝缘膜沉积在晶片上。 然后在低k电介质膜上沉积金属层。 在金属层上形成抗蚀剂图案。 然后将抗蚀剂图案转移到下面的金属层以形成金属图案。 剥离抗蚀剂图案。 通过使用金属图案作为硬掩模将通孔等离子体蚀刻到低k电介质膜中。 等离子体蚀刻导致残留物沉积在通孔内。 然后进行湿处理以软化残留物。 进行等离子体干燥处理以破坏残留物。

公开(公告)号：US20070111514A1

公开(公告)日：2007-05-17

申请号：US11164285

申请日：2005-11-17

申请人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

发明人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

IPC分类号： H01L21/473

CPC分类号： H01L21/7681 ,  H01L21/76829

摘要： A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

摘要翻译： 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

公开(公告)号：US07214612B2

公开(公告)日：2007-05-08

申请号：US11162154

申请日：2005-08-31

申请人： Jen-Ren Huang ,  Cheng-Ming Weng ,  Miao-Chun Lin

发明人： Jen-Ren Huang ,  Cheng-Ming Weng ,  Miao-Chun Lin

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76813

摘要： A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.

摘要翻译： 描述了一种双镶嵌结构，包括基底，电介质层，硬掩模层，触点和导电线。 电介质层位于基板上，硬掩模层位于电介质层上，触点位于电介质层中，触头的水平横截面具有不对称的圆形轮廓。 导电线位于硬掩模层和介电层中，并且位于触点上并电连接。 导线在第一接触件的边缘部分上具有横向膨胀部分，其中横向膨胀部分和边缘部分的边界是连续的。

公开(公告)号：US20070080386A1

公开(公告)日：2007-04-12

申请号：US11608252

申请日：2006-12-08

申请人： Jen-Ren Huang ,  Cheng-Ming Weng ,  Miao-Chun Lin

发明人： Jen-Ren Huang ,  Cheng-Ming Weng ,  Miao-Chun Lin

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L21/76811 ,  H01L21/76813

摘要： A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.

摘要翻译： 描述了一种双镶嵌结构，包括基底，电介质层，硬掩模层，触点和导电线。 电介质层位于基板上，硬掩模层位于电介质层上，触点位于电介质层中，触头的水平横截面具有不对称的圆形轮廓。 导电线位于硬掩模层和电介质层中，并且位于触点上并电连接。 导线在第一接触件的边缘部分上具有横向膨胀部分，其中横向膨胀部分和边缘部分的边界是连续的。

公开(公告)号：US20080121619A1

公开(公告)日：2008-05-29

申请号：US11562989

申请日：2006-11-23

申请人： Miao-Chun Lin ,  Cheng-Ming Weng ,  Chun-Jen Huang

发明人： Miao-Chun Lin ,  Cheng-Ming Weng ,  Chun-Jen Huang

IPC分类号： C23F1/00 ,  B08B3/08 ,  B08B5/00

CPC分类号： H01L21/02063 ,  H01L21/76807 ,  H01L21/76814 ,  Y10S134/902 ,  Y10S438/906

摘要： A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.

摘要翻译： 提供了在蚀刻处理之后清洁晶片的方法。 提供了具有蚀刻停止层，电介质层，依次形成的图案化金属硬掩模的基板。 使用图案化金属硬掩模，在介电层中限定开口。 开口露出一部分蚀刻停止层。 在氦气的环境中进行干蚀刻处理以除去由开口露出的蚀刻停止层。 使用氮和氢的混合物作为反应气体在晶片表面上进行干洗处理。 使用含有微量氢氟酸的清洗溶液在晶片表面上进行湿式清洗处理。

公开(公告)号：US07192878B2

公开(公告)日：2007-03-20

申请号：US10908374

申请日：2005-05-09

申请人： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

发明人： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31144 ,  H01L21/02063 ,  H01L21/76811 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/963

摘要： A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A first wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues. A second wet treatment is performed to completely remove the residues.

摘要翻译： 低k绝缘膜沉积在晶片上。 然后在低k电介质膜上沉积金属层。 在金属层上形成抗蚀剂图案。 然后将抗蚀剂图案转移到下面的金属层以形成金属图案。 剥离抗蚀剂图案。 通过使用金属图案作为硬掩模将通孔等离子体蚀刻到低k电介质膜中。 等离子体蚀刻导致残留物沉积在通孔内。 然后进行第一次湿处理以软化残留物。 进行等离子体干燥处理以破坏残留物。 进行第二次湿处理以完全去除残留物。

公开(公告)号：US20070052107A1

公开(公告)日：2007-03-08

申请号：US11162272

申请日：2005-09-05

申请人： Cheng-Ming Weng ,  Miao-Chun Lin

发明人： Cheng-Ming Weng ,  Miao-Chun Lin

IPC分类号： H01L23/48

CPC分类号： H01L23/53238 ,  H01L21/76829 ,  H01L23/53223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene structure comprising a substrate, a dielectric layer, a metal hard mask layer, a protection layer and a conductive layer is provided. The substrate has a conductive area. The dielectric layer is disposed on the substrate. The metal hard mask layer is disposed on the dielectric layer. The protection layer is disposed on the metal hard mask layer. A trench is disposed in the protection layer, the metal hard mask layer and a part of the dielectric layer. An opening is disposed in the dielectric layer under the trench. The opening exposes the conductive area. The conductive layer is disposed in the trench and the opening.

摘要翻译： 提供了一种双镶嵌结构，其包括基底，电介质层，金属硬掩模层，保护层和导电层。 基板具有导电区域。 电介质层设置在基板上。 金属硬掩模层设置在电介质层上。 保护层设置在金属硬掩模层上。 沟槽设置在保护层中，金属硬掩模层和电介质层的一部分。 开口设置在沟槽下面的电介质层中。 开口暴露导电区域。 导电层设置在沟槽和开口中。

公开(公告)号：US20070049012A1

公开(公告)日：2007-03-01

申请号：US11162154

申请日：2005-08-31

申请人： Jen-Ren Huang ,  Cheng-Ming Weng ,  Miao-Chun Lin

发明人： Jen-Ren Huang ,  Cheng-Ming Weng ,  Miao-Chun Lin

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76813

摘要： A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.

摘要翻译： 描述了一种双镶嵌结构，包括基底，电介质层，硬掩模层，触点和导电线。 电介质层位于基板上，硬掩模层位于电介质层上，触点位于电介质层中，触头的水平横截面具有不对称的圆形轮廓。 导电线位于硬掩模层和介电层中，并且位于触点上并电连接。 导线在第一接触件的边缘部分上具有横向膨胀部分，其中横向膨胀部分和边缘部分的边界是连续的。

公开(公告)号：US20060252256A1

公开(公告)日：2006-11-09

申请号：US10908374

申请日：2005-05-09

申请人： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

发明人： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/02063 ,  H01L21/76811 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/963

摘要： A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A first wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues. A second wet treatment is performed to completely remove the residues.

摘要翻译： 低k绝缘膜沉积在晶片上。 然后在低k电介质膜上沉积金属层。 在金属层上形成抗蚀剂图案。 然后将抗蚀剂图案转移到下面的金属层以形成金属图案。 剥离抗蚀剂图案。 通过使用金属图案作为硬掩模将通孔等离子体蚀刻到低k电介质膜中。 等离子体蚀刻导致残留物沉积在通孔内。 然后进行第一次湿处理以软化残留物。 进行等离子体干燥处理以破坏残留物。 进行第二次湿处理以完全去除残留物。