公开(公告)号：US08470628B2

公开(公告)日：2013-06-25

申请号：US13164126

申请日：2011-06-20

申请人： Michael A Guillorn ,  Eric A Joseph ,  Fei Liu ,  Zhen Zhang

发明人： Michael A Guillorn ,  Eric A Joseph ,  Fei Liu ,  Zhen Zhang

IPC分类号： H01L21/66

CPC分类号： B81C1/00666 ,  B81C1/00952 ,  H01H1/0094 ,  H01H2001/0078

摘要： A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a silicon layer disposed over an insulating layer that is disposed on a silicon substrate; releasing a portion of the silicon layer from the insulating layer so that it is at least partially suspended over a cavity in the insulating layer; depositing a metal (e.g., Pt) on at least one surface of at least the released portion of the silicon layer and, using a thermal process, fully siliciding at least the released portion of the silicon layer using the deposited metal. The method eliminates silicide-induced stress to the released Si member, as the entire Si member is silicided. Furthermore no conventional wet chemical etch is used after forming the fully silicided material thereby reducing a possibility of causing corrosion of the silicide and an increase in stiction.

摘要翻译： 公开了一种制造诸如MEMS或NEMS开关的机电装置的方法。 该方法包括提供设置在设置在硅衬底上的绝缘层上的硅层; 从所述绝缘层释放所述硅层的一部分，使得其至少部分地悬挂在所述绝缘层中的空腔上; 在至少所述硅层的释放部分的至少一个表面上沉积金属（例如Pt），并且使用热处理，使用沉积的金属至少完全硅化硅层的释放部分。 当整个Si元件被硅化时，该方法消除了对释放的Si元件的硅化物引起的应力。 此外，在形成完全硅化材料之后，也不使用常规的湿化学蚀刻，从而减少引起硅化物腐蚀和粘性增加的可能性。

公开(公告)号：US08440523B1

公开(公告)日：2013-05-14

申请号：US13313163

申请日：2011-12-07

申请人： Michael A Guillorn ,  Fei Liu ,  Ying Zhang

发明人： Michael A Guillorn ,  Fei Liu ,  Ying Zhang

IPC分类号： H01L21/8242

CPC分类号： B81C1/00396 ,  B81B2201/018 ,  B81B2207/015 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0132 ,  H01H1/0036 ,  H01H1/0094

摘要： A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a structure composed of a silicon layer disposed over an insulating layer that is disposed on a silicon substrate. The silicon layer is differentiated into a partially released region that will function as a portion of the electro-mechanical device. The method further includes forming a dielectric layer over the silicon layer; forming a hardmask over the dielectric layer, the hardmask being composed of hafnium oxide; opening a window to expose the partially released region; and fully releasing the partially released region using a dry etching process to remove the insulating layer disposed beneath the partially released region while using the hardmask to protect material covered by the hardmask. The step of fully releasing can be performed using a HF vapor.

摘要翻译： 公开了一种制造诸如MEMS或NEMS开关的机电装置的方法。 该方法包括提供由设置在硅衬底上的绝缘层上的硅层构成的结构。 硅层被分化为部分释放的区域，其将用作机电装置的一部分。 该方法还包括在硅层上形成电介质层; 在介电层上形成硬掩模，硬掩模由氧化铪组成; 打开窗户露出部分释放的地区; 并且使用干蚀刻工艺完全释放部分释放的区域，以在使用硬掩模来去除设置在部分释放区域下方的绝缘层以保护由硬掩模覆盖的材料。 完全释放的步骤可以使用HF蒸汽进行。

公开(公告)号：US20100295022A1

公开(公告)日：2010-11-25

申请号：US12470159

申请日：2009-05-21

申请人： Josephine Chang ,  Paul Chang ,  Michael A Guillorn ,  Jeffrey Sleight

发明人： Josephine Chang ,  Paul Chang ,  Michael A Guillorn ,  Jeffrey Sleight

IPC分类号： H01L29/66 ,  H01L21/3205 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.

摘要翻译： 提供了基于纳米线的场效应晶体管（FET）及其制造技术。 在一个方面，提供了一种FET，其具有在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个 的器件层被配置为具有来自一个或多个其它器件层的不同阈值电压; 以及围绕纳米线通道的每个器件层共用的栅极。

公开(公告)号：US08637371B2

公开(公告)日：2014-01-28

申请号：US13398339

申请日：2012-02-16

申请人： Josephine B Chang ,  Paul Chang ,  Michael A Guillorn ,  Chung-hsun Lin ,  Jeffrey W Sleight

发明人： Josephine B Chang ,  Paul Chang ,  Michael A Guillorn ,  Chung-hsun Lin ,  Jeffrey W Sleight

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/0657 ,  H01L29/66795

摘要： Non-planar Metal Oxide Field Effect Transistors (MOSFETs) and methods for making non-planar MOSFETs with asymmetric, recessed source and drains having improved extrinsic resistance and fringing capacitance. The methods include a fin-last, replacement gate process to form the non-planar MOSFETs and employ a retrograde metal lift-off process to form the asymmetric source/drain recesses. The lift-off process creates one recess which is off-set from a gate structure while a second recess is aligned with the structure. Thus, source/drain asymmetry is achieved by the physical structure of the source/drains, and not merely by ion implantation. The resulting non-planar device has a first channel of a fin contacting a substantially undoped area on the drain side and a doped area on the source side, thus the first channel is asymmetric. A channel on atop surface of a fin is symmetric because it contacts doped areas on both the drain and source sides.

摘要翻译： 非平面金属氧化物场效应晶体管（MOSFET）和用于制造具有改进的外在电阻和边缘电容的具有不对称，凹陷源极和漏极的非平面MOSFET的方法。 这些方法包括最后一个替代栅极工艺，以形成非平面MOSFET并且采用逆向金属剥离工艺来形成不对称的源极/漏极凹槽。 剥离过程产生一个从门结构偏离的凹槽，而第二凹槽与结构对准。 因此，源/漏不对称性通过源极/漏极的物理结构实现，而不仅仅是通过离子注入来实现。 所得到的非平面器件具有接触漏极侧的基本上未掺杂的区域和源极侧的掺杂区域的翅片的第一通道，因此第一通道是不对称的。 鳍的顶表面上的通道是对称的，因为它接触漏极和源极侧上的掺杂区域。