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    SAM data selection on dual-ported DRAM devices
    3.
    发明授权
    SAM data selection on dual-ported DRAM devices 失效
    双端口DRAM设备上的SAM数据选择

    公开(公告)号：US5257237A

    公开(公告)日：1993-10-26

    申请号：US791666

    申请日：1991-11-12

    申请人： Michael A. Aranda ,  Andrew D. Bowen ,  Timothy J. Ebbers ,  Randall L. Henderson ,  Nathan R. Hiltebeitel ,  Robert Tamlyn

    发明人： Michael A. Aranda ,  Andrew D. Bowen ,  Timothy J. Ebbers ,  Randall L. Henderson ,  Nathan R. Hiltebeitel ,  Robert Tamlyn

    IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C11/4096

    CPC分类号： G11C11/4096 ,  G11C7/1075 ,  G11C8/00

    摘要： The selection in a dual port memory device of data from a serial access memory register having a lower byte and an upper byte of data is described herein. In one embodiment, the register is partitioned lengthwise into two sections, corresponding to, for example, a frame buffer A and a frame buffer B. On each serial clock cycle, frame buffer A or frame buffer B for each byte of data may be selected from the register. Each of the selected bytes of data are then passed to a serial output port. In another embodiment, the lower byte of data corresponds to, for example, a frame buffer A and the upper byte corresponds to a frame buffer B. Then either the upper byte or lower byte of data is selected to be output on the serial port. In yet a further embodiment, the serial access memory register is partitioned lengthwise into two sections, each section corresponding to, for example, a frame buffer and the bytes of data correspond to another buffer, then either the lower byte or upper byte is selected to be output on the serial port.

    摘要翻译： 这里描述了具有低字节和高字节数​​据的串行访问存储器寄存器的双端口存储器件中的数据的选择。 在一个实施例中，寄存器被纵向分割成对应于例如帧缓冲器A和帧缓冲器B的两个部分。在每个串行时钟周期上，可以选择每个数据字节的帧缓冲器A或帧缓冲器B 从登记册。 然后将每个选定的数据字节传递给串行输出端口。 在另一个实施例中，数据的低字节对应于例如帧缓冲器A，高字节对应于帧缓冲器B.然后选择数据的高字节或低字节在串行端口上输出。 在又一个实施例中，串行访问存储器寄存器被纵向划分为两个部分，每个部分对应于例如帧缓冲器，并且数据字节对应于另一个缓冲器，则低字节或高字节被选择为 在串口上输出。

    Multiplexed serial register architecture for VRAM
    4.
    发明授权
    Multiplexed serial register architecture for VRAM 失效
    用于VRAM的多路复用串行寄存器架构

    公开(公告)号：US4984214A

    公开(公告)日：1991-01-08

    申请号：US446032

    申请日：1989-12-05

    申请人： Nathan R. Hiltebeitel ,  Robert Tamlyn ,  Steven W. Tomashot

    发明人： Nathan R. Hiltebeitel ,  Robert Tamlyn ,  Steven W. Tomashot

    IPC分类号： G11C11/401 ,  G11C11/4096

    CPC分类号： G11C11/4096

    摘要： A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

    Flexible redundancy architecture and fuse download scheme
    5.
    发明授权
    Flexible redundancy architecture and fuse download scheme 失效
    灵活的冗余架构和保险丝下载方案

    公开(公告)号：US5430679A

    公开(公告)日：1995-07-04

    申请号：US119797

    申请日：1993-09-10

    申请人： Nathan R. Hiltebeitel ,  Dale E. Pontius ,  Steven W. Tomashot

    发明人： Nathan R. Hiltebeitel ,  Dale E. Pontius ,  Steven W. Tomashot

    IPC分类号： G06F11/16 ,  G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  H01H85/00 ,  G11C7/00

    CPC分类号： G11C29/785 ,  G11C29/808

    摘要： A fuse download system for programming decoders for redundancy. Auxiliary fuse banks have sets of fuses that store logic states that (a) select a redundant decoder and (b) indicate the address of a faulty row/column of memory cells. When the chip is first powered up, each set of fuses is accessed and downloaded to program selected redundant decoders. Because the fuse sets can be dynamically assigned to redundant decoders on an any-for-any basis, the fault tolerance of the redundancy system is enhanced.

    摘要翻译： 用于冗余编程解码器的熔丝下载系统。 辅助保险丝组有一组保险丝，存储逻辑状态，（a）选择冗余解码器，（b）指示存储器单元故障行/列的地址。 当芯片首次通电时，每组保险丝被访问并下载到程序中选择的冗余解码器。 由于可以在任何情况下将熔丝组动态分配给冗余解码器，故冗余系统的容错能力得到提高。

    Low voltage programmable storage element
    6.
    发明授权
    Low voltage programmable storage element 失效
    低电压可编程存储元件

    公开(公告)号：US5418738A

    公开(公告)日：1995-05-23

    申请号：US221515

    申请日：1994-04-01

    申请人： Wagdi W. Abadeer ,  Badih El-Kareh ,  Wayne F. Ellis ,  Duane E. Galbi ,  Nathan R. Hiltebeitel ,  William R. Tonti ,  Josef S. Watts

    发明人： Wagdi W. Abadeer ,  Badih El-Kareh ,  Wayne F. Ellis ,  Duane E. Galbi ,  Nathan R. Hiltebeitel ,  William R. Tonti ,  Josef S. Watts

    IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C17/00 ,  G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  G11C29/00 ,  G11C29/04 ,  H01L27/10

    CPC分类号： G11C29/785 ,  G11C17/14 ,  G11C17/16

    摘要： A programmable storage element for redundancy-programing includes a programmable antifuse circuit, which includes a plurality of first resistors and a switching circuit for coupling the first resistors in series in response to a plurality of first control signals and for coupling the first resistors in parallel in response to a plurality of second control signals to permit programing of the first resistors, and a sensing circuit for determining whether or not the first resistors have been programmed. The state of the first resistors is determined by comparing a first voltage drop across the first resistors with a second voltage drop across a second resistor. Each of the first resistors is an unsilicided polysilicon conductor which has an irreversible resistance decrease when a predetermined threshold current is applied for a minimum period of time.

    摘要翻译： 用于冗余编程的可编程存储元件包括可编程反熔丝电路，其包括多个第一电阻器和用于响应于多个第一控制信号串联耦合第一电阻器并用于将第一电阻器并联耦合的开关电路 响应于多个第二控制信号以允许编程第一电阻器，以及用于确定第一电阻器是否已被编程的感测电路。 第一电阻器的状态通过将第一电阻器两端的第一电压降与第二电阻器上的第二电压降进行比较来确定。 每个第一电阻器是非极性多晶硅导体，当预定阈值电流施加最小时间时，其具有不可逆电阻降低。