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公开(公告)号：US4256972A
公开(公告)日：1981-03-17
申请号：US37680
申请日：1979-05-10
CPC分类号： G01R29/18 , H02J3/42 , Y10T307/615 , Y10T307/636 , Y10T307/647 , Y10T307/735 , Y10T307/839
摘要： Power transfer relay circuitry is disclosed for providing synchronous transfer of power such as from an auxiliary source or system to a motor or motor bus; the circuitry effects the transfer of power when the phase difference between the motor bus and the auxiliary power source is very nearly zero degrees.
摘要翻译： 公开了功率传递继电器电路，用于提供诸如从辅助源或系统到电动机或电动机总线的电力的同步传递; 当电机总线和辅助电源之间的相位差非常接近零度时，电路会影响功率传递。
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公开(公告)号：US4310771A
公开(公告)日：1982-01-12
申请号：US37703
申请日：1979-05-10
CPC分类号： G01R29/18 , H02J3/42 , Y10T307/615 , Y10T307/636 , Y10T307/647 , Y10T307/735 , Y10T307/839
摘要： In a typical power system, a motor bus is fed by a main power system; and, an auxiliary system is provided to alternatively feed the motor bus. When a fast transfer from the main power to the auxiliary power system is desired, for example, in case of fault occurring in the main system, the inventive method transfers power in a synchronous mode; that is, power is transferred from the auxiliary system to the motor bus when the phase difference of the auxiliary system with respect to the frequency of the residual voltage on the motor bus is essentially zero degrees.
摘要翻译： 在典型的电力系统中，电动车总线由主电力系统供电; 并且提供辅助系统以交替地供给马达总线。 当需要从主电源到辅助电力系统的快速传送时，例如，在主系统中发生故障的情况下，本发明的方法以同步模式传送电力; 即当辅助系统相对于马达总线上的残余电压的频率的相位差基本上为零度时，电力从辅助系统传递到马达总线。
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公开(公告)号：US4218625A
公开(公告)日：1980-08-19
申请号：US872268
申请日：1978-01-25
CPC分类号： H02J3/08 , H02H11/00 , Y10T307/735
摘要： A synchronizing check relay is used in an electrical transmission network for controlling a circuit breaker to interconnect first and second transmission lines to establish power flow therebetween and includes an input circuit for receiving signals from first and second transmission lines. A phase difference generator generates a phase difference signal proportional to a phase difference between said signals from said first and second transmission lines. A phase difference comparator receives the phase difference signal and produces a phase output signal at a selected phase condition. An adjustable timer produces a timer signal after a selected time interval in response to the phase comparator to insure a proper phase difference between the transmission lines. The voltage sensor produces a breaker closing inhibit signal when one of the alternating current voltages is outside a reference limit. A control circuit is responsive to the phase output signal, the time signal and the breaker closing inhibit signal for providing a control response to the circuit breaker.
摘要翻译： 在电传输网络中使用同步检查继电器，用于控制断路器以互连第一和第二传输线路以在其间建立功率流，并且包括用于从第一和第二传输线路接收信号的输入电路。 相位差发生器产生与来自所述第一和第二传输线的所述信号之间的相位差成比例的相位差信号。 相位差比较器接收相位差信号，并在所选择的相位条件下产生相位输出信号。 可调定时器响应于相位比较器在选定的时间间隔之后产生定时器信号，以确保传输线之间的适当的相位差。 当交流电压之一超过参考极限时，电压传感器产生断路器闭合禁止信号。 控制电路响应相位输出信号，时间信号和断路器闭合禁止信号，以提供对断路器的控制响应。
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4.发明申请公开(公告)号：US20080001665A1
公开(公告)日：2008-01-03
申请号：US11504425
申请日：2006-08-15
申请人： Michael A. Wyatt
发明人： Michael A. Wyatt
IPC分类号： H03F3/45
CPC分类号： H03F3/195 , H03F1/42 , H03F3/45 , H03F3/45085 , H03F3/45475 , H03F2200/36 , H03F2203/45136 , H03F2203/45466 , H03F2203/45638
摘要： A wideband splitter includes a core amplifier for receiving a single pair of differential input signals and providing first and second pairs of differential output signals. The first pair of differential output signals and the second pair of differential outputs have substantially identical characteristics. A signal gain is implemented between the received single pair of differential input signals and the first and second pair of differential output signals. The signal gain is substantially constant across the frequency bandwidth of the core amplifier. A bandwidth peaking network is coupled to the core amplifier and includes (a) a first coil and a first resistor connected in series and (b) a second coil and a second resistor connected in series. The bandwidth peaking network is configured to increase the frequency bandwidth of the core amplifier.
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5.发明授权Serrodyne phase modulator having ramp generated by combining two oscillator signals 失效Serrodyne相位调制器具有通过组合两个振荡器信号产生的斜坡
公开(公告)号：US5339055A
公开(公告)日：1994-08-16
申请号：US992551
申请日：1992-12-18
申请人： Michael A. Wyatt
发明人： Michael A. Wyatt
CPC分类号： H03C3/00
摘要： A frequency phase modulator which generates a phase modulator controlled slope voltage waveform. The controlled slope voltage waveform is controlled by coupling a first fixed frequency oscillator with a second variable frequency voltage controlled oscillator. The period of the ramp waveform (slope) is equal to the difference between the two frequencies. The phases of the two oscillators are compared and integrated to produce the phase modulator ramp waveform.
摘要翻译： 一个频率相位调制器，产生相位调制器控制的斜坡电压波形。 通过将第一固定频率振荡器与第二可变频率压控振荡器耦合来控制受控斜率电压波形。 斜坡波形（斜率）的周期等于两个频率之间的差。 将两个振荡器的相位进行比较和积分，以产生相位调制器斜坡波形。
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6.发明授权Ultra wide band, differential input/output, high frequency active mixer in an integrated circuit 有权超宽带，差分输入/输出，高频有源混频器在集成电路中公开(公告)号：US07587187B2
公开(公告)日：2009-09-08
申请号：US11504426
申请日：2006-08-15
申请人： Michael A. Wyatt
发明人： Michael A. Wyatt
IPC分类号： H04B1/06
CPC分类号： H03C3/222
摘要： A wideband mixer includes a core mixer having input terminals and output terminals for, respectively, receiving differential input signals and providing amplified differential output signals. A steering module is coupled to the core mixer for receiving differential reference signals and providing bi-phase modulated amplified differential output signals. The core mixer is configured to provide a value of gain between the differential input signals and the differential output signals. A bandwidth peaking network is coupled to the core mixer and includes (a) a first coil and a first resistor connected in series and (b) a second coil and a second resistor connected in series. The first coil and resistor and the second coil and resistor, respectively, are coupled to the core mixer for receiving the amplified differential output signals. The bandwidth peaking network is configured to increase the frequency bandwidth of the core mixer.
摘要翻译： 宽带混频器包括具有输入端和核心混频器，输入端分别用于接收差分输入信号并提供放大的差分输出信号。 转向模块耦合到核心混频器，用于接收差分参考信号并提供双相调制放大的差分输出信号。 核心混频器被配置为提供差分输入信号和差分输出信号之间的增益值。 带宽峰化网络耦合到核心混频器，并且包括（a）串联连接的第一线圈和第一电阻器，以及串联连接的第二线圈和第二电阻器。 第一线圈和电阻器以及第二线圈和电阻器分别耦合到核心混频器，用于接收放大的差分输出信号。 带宽峰值网络被配置为增加核心混频器的频率带宽。
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公开(公告)号：US20090108866A1
公开(公告)日：2009-04-30
申请号：US11926622
申请日：2007-10-29
申请人： Michael A. Wyatt
发明人： Michael A. Wyatt
IPC分类号： H03K19/003
CPC分类号： H03K19/0033 , H03K19/09418
摘要： A radiation hardened inverter includes first and second electrical paths between an input terminal and an output terminal. A first PFET is disposed in the first electrical path, and a bipolar junction transistor (BJT) is disposed in the second electrical path. The first PFET is configured to convert a low level signal at the input terminal to a high level signal at the output terminal, and the BJT is configured to convert a high level signal at the input terminal to a low level signal at the output terminal. The radiation hardened inverter includes a second PFET disposed in the second electrical path. The second PFET is configured to provide a path for bleeding excess current away from the BJT. The radiation hardened inverter also includes a current limiting PFET disposed in the second electrical path. The current limiting PFET is configured to limit current flowing into a base of the BJT. The radiation hardened inverter is free-of any NFETs.
摘要翻译： 辐射硬化的逆变器包括在输入端子和输出端子之间的第一和第二电路径。 第一PFET设置在第一电路中，并且双极结型晶体管（BJT）设置在第二电路中。 第一PFET被配置为将输入端子处的低电平信号转换为输出端子处的高电平信号，并且BJT被配置为将输入端子处的高电平信号转换为输出端子处的低电平信号。 辐射硬化逆变器包括设置在第二电路中的第二PFET。 第二PFET被配置为提供用于将过剩电流从BJT流出的路径。 放射硬化逆变器还包括设置在第二电路中的限流PFET。 限流PFET被配置为限制流入BJT的基极的电流。 辐射硬化逆变器不含任何NFET。
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8.发明授权Ultra wide band, differential input/output, high frequency active splitter in an integrated circuit 有权超宽带，差分输入/输出，集成电路中的高频有源分路器公开(公告)号：US07400193B2
公开(公告)日：2008-07-15
申请号：US11504425
申请日：2006-08-15
申请人： Michael A. Wyatt
发明人： Michael A. Wyatt
IPC分类号： H03F3/00
CPC分类号： H03F3/195 , H03F1/42 , H03F3/45 , H03F3/45085 , H03F3/45475 , H03F2200/36 , H03F2203/45136 , H03F2203/45466 , H03F2203/45638
摘要： A wideband splitter includes a core amplifier for receiving a single pair of differential input signals and providing first and second pairs of differential output signals. The first pair of differential output signals and the second pair of differential outputs have substantially identical characteristics. A signal gain is implemented between the received single pair of differential input signals and the first and second pair of differential output signals. The signal gain is substantially constant across the frequency bandwidth of the core amplifier. A bandwidth peaking network is coupled to the core amplifier and includes (a) a first coil and a first resistor connected in series and (b) a second coil and a second resistor connected in series. The bandwidth peaking network is configured to increase the frequency bandwidth of the core amplifier.
摘要翻译： 宽带分离器包括用于接收单对差分输入信号的核心放大器，并提供第一和第二对差分输出信号。 第一对差分输出信号和第二对差分输出具有基本相同的特性。 在接收到的一对差分输入信号与第一和第二对差分输出信号之间实现信号增益。 信号增益在芯放大器的频率带宽上基本恒定。 带宽峰化网络耦合到核心放大器，并且包括（a）串联连接的第一线圈和第一电阻器，以及串联连接的第二线圈和第二电阻器。 带宽峰化网络被配置为增加核心放大器的频率带宽。
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公开(公告)号：US5909147A
公开(公告)日：1999-06-01
申请号：US934029
申请日：1997-09-19
申请人： Michael A. Wyatt
发明人： Michael A. Wyatt
摘要： An RF amplifier has multiple DC coupled gain stages which generate an output signal by amplifying an input RF signal. All of the transistors are NPN and directly coupled through filters. The amplifier input and output stages actively match the impedance of the RF source and load.
摘要翻译： RF放大器具有多个直流耦合增益级，通过放大输入RF信号来产生输出信号。 所有晶体管都是NPN，并通过滤波器直接耦合。 放大器输入和输出级主动匹配RF源和负载的阻抗。
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10.发明授权High power and high frequency gallium nitride based digital to analog converter for direct digital radio frequency power waveform synthesis 有权大功率和高频氮化镓基数字到模拟转换器，用于直接数字射频功率波形合成公开(公告)号：US07903016B1
公开(公告)日：2011-03-08
申请号：US12539929
申请日：2009-08-12
申请人： Michael A. Wyatt
发明人： Michael A. Wyatt
IPC分类号： H03M1/80
CPC分类号： H03M1/745
摘要： A high power digital to analog converter (DAC) includes (a) an array of n bipolar transistors arranged in a binary sequence, (b) a depletion mode FET and (c) an array of n switches. The collector terminals of each bipolar transistor in the array are tied together. Furthermore, the depletion mode FET includes a source terminal which is directly connected to the collector terminals of each bipolar transistor. The FET also includes a gate terminal connected to a ground potential, and a drain terminal. Each bipolar transistor is sized to be a factor larger than its preceding transistor in the array of n bipolar transistors, for example, twice as large. The array of n switches is controlled by a digital word of n bits. Each of the n switches selectively activates a respective bipolar transistor in the array of n bipolar transistors. As the n switches are selectively activated, the array of n bipolar transistors provides n binary weighted collector currents in the source terminal of the FET. The n collector currents are equal to a sum of the binary weighted collector currents. The drain terminal of the FET provides the same sum of the binary weighted collector currents.
摘要翻译： 高功率数模转换器（DAC）包括（a）以二进制序列排列的n双极晶体管阵列，（b）耗尽型FET和（c）n个开关阵列。 阵列中每个双极晶体管的集电极端子被连接在一起。 此外，耗尽型FET包括直接连接到每个双极晶体管的集电极端子的源极端子。 FET还包括连接到地电位的栅极端子和漏极端子。 每个双极晶体管的尺寸设定为比n个双极晶体管的阵列中的前一晶体管大的一个因数，例如两倍大。 n个开关的阵列由n位的数字字来控制。 n个开关中的每一个选择性地激活n个双极晶体管阵列中的相应双极晶体管。 当n个开关被选择性地激活时，n个双极晶体管的阵列在FET的源极端子中提供n个二进制加权的集电极电流。 n个集电极电流等于二进制加权集电极电流的总和。 FET的漏极端子提供相同的二进制加权集电极电流之和。
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