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公开(公告)号：US10026151B2
公开(公告)日：2018-07-17
申请号：US15024774
申请日：2013-09-27
摘要： A script-driven head-up display controller comprising an image warping unit and an image projection unit wherein the image warping unit is coupled to the image projection unit and is adapted to: receive a line-based warping descriptor comprising first information associated with a distortion caused by a non-flat display; and, in response to the reception of the line-based warping descriptor, the image warping unit is further adapted to, based on the line-based warping descriptor: fetch one or more lines of the source image; and, output to the image projection unit at least one output line of the output image associated with an electronic image warping of one or more pixels of the one or more input lines, and wherein the line-based warping descriptor further comprises second information associated with buffer management instructions calculated off-line.
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公开(公告)号：US09805432B2
公开(公告)日：2017-10-31
申请号：US14479456
申请日：2014-09-08
IPC分类号： G06T1/00 , G06K9/00 , G07C5/08 , G08B13/196
CPC分类号： G06T1/0007 , G06K9/00926 , G07C5/0866 , G07C5/0891 , G08B13/19676
摘要： A data logging system for logging input data received from a data source is described. The data logging system has a data storage memory. A data input is arranged to repeatedly receive input data having a temporal input data resolution. A write controller is arranged to write newly received input data as received via the data input into the data storage memory. The writing comprises writing the newly received input data at the temporal input data resolution. The writing comprises keeping recent data at the temporal input data resolution in the data storage memory, and overwriting part of old data with newly received input data while keeping another part of the old data in the data storage memory at lower data resolution.
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公开(公告)号：US09641809B2
公开(公告)日：2017-05-02
申请号：US14224167
申请日：2014-03-25
摘要： The present invention relates to a circuit arrangement for processing a digital video stream, the circuit arrangement comprising: an input interface for receiving a digital video stream, a processing circuit which is arranged to process the digital video stream, a hang-up detecting circuit for detecting a fault in the processed digital video stream, the hang-up detecting circuit comprising: a checksum generating circuit which is arranged to generate checksums for the frames of the processed digital video stream, a memory for storing generated checksums and an analyzing device arranged to compare a currently generated checksum to a plurality of corresponding checksums of preceding frames stored in the memory and to generate an error signal if at least one predefined amount of compared checksums are matching. The present invention also relates to a digital video system, a method for processing a digital video stream and a computer readable program product.
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公开(公告)号：US09558373B2
公开(公告)日：2017-01-31
申请号：US14563139
申请日：2014-12-08
摘要： A 3D graphics system uses encryption keys to decrypt received and stored texture tiles of a texture in accordance with received and stored texture tile status data which indicates whether a texture tiles is encrypted or not and which one of the encryption keys is used. The decrypted texture tiles are rendered and at least a plurality of the rendered tiles is encrypted. The encrypted rendered tiles are stored in a frame buffer. Buffer tile status data is stored which indicates whether a rendered tile is encrypted or not before storage in the frame buffer, and which one of the encryption keys has been used. The encrypted rendered tiles stored in the frame buffer are decrypted in accordance with the buffer tile status data.
摘要翻译： 3D图形系统使用加密密钥来根据接收和存储的纹理瓦片状态数据来解密纹理的接收和存储的纹理瓦片，该纹理瓦片状态数据指示纹理瓦片是否被加密，以及使用哪个加密密钥。 解密的纹理图块被渲染，并且至少多个渲染的图块被加密。 加密的渲染瓦片被存储在帧缓冲器中。 存储缓冲区块状态数据，其指示在帧缓冲器中存储之前是否加密了已渲染的块，并且已经使用了哪个加密密钥。 存储在帧缓冲器中的加密渲染瓦片根据缓冲器瓦片状态数据被解密。
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公开(公告)号：US09232156B1
公开(公告)日：2016-01-05
申请号：US14492573
申请日：2014-09-22
摘要： A video processing device for generating an output video stream on the basis of two or more concurrent input video streams and a method thereof are described. Each input video stream comprises a sequence of input images. The output video stream comprises a sequence of output images. The video processing device generates each output image by merging a respective set of input images. The set of input images comprises one input image from each input video stream. The video processing device merges the input images in a series of merging rounds. Each merging round comprises forming an output tile by merging a set of input tiles, and writing the output tile to an output memory unit. The set of input tiles comprises one input tile from each input image of the respective set of input images. The output tiles written to the output memory unit represent the output image.
摘要翻译： 描述了用于基于两个或多个并发输入视频流生成输出视频流的视频处理设备及其方法。 每个输入视频流包括一系列输入图像。 输出视频流包括一系列输出图像。 视频处理装置通过合并各组输入图像来生成每个输出图像。 该组输入图像包括来自每个输入视频流的一个输入图像。 视频处理设备在一系列合并回合中合并输入图像。 每个合并包括通过合并一组输入瓦片形成输出瓦片，以及将输出瓦片写入输出存储器单元。 该组输入图块包括来自相应输入图像集合的每个输入图像的一个输入图块。 写入输出存储单元的输出贴片表示输出图像。
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公开(公告)号：US10147463B2
公开(公告)日：2018-12-04
申请号：US14708947
申请日：2015-05-11
摘要： In a video system, a video source, e.g., a camera, provides a source video stream. The source video stream comprises a stream of image data units. A buffer control unit writes the image data units consecutively to a circular buffer. A display control unit reads the image data units consecutively from the circular buffer to generate a target video stream in accordance with a read delay. The display control unit comprises a feedback loop which controls timing of the operation of reading the image data units from the circular buffer so as to reduce a difference between the read delay and a reference delay. The video system may, for example, be installed in a vehicle, e.g., for providing a driver with a live view from a camera.
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公开(公告)号：US10074154B2
公开(公告)日：2018-09-11
申请号：US14709680
申请日：2015-05-12
CPC分类号： G06T1/60 , G06F5/065 , G06F13/1673 , G06F13/404 , G06F13/4282 , G06F2205/067
摘要： A display controller comprises a plurality of channels for fetching data from a memory, a plurality of buffers coupled to the channels for receiving the fetched data from the channels, a buffer controller for controlling the buffers and the channels, and a processing unit coupled to the buffers, the display and buffer controller for receiving the data from the buffers, outputting a control signal to the display based on the received data, and controlling the buffer controller, respectively. Each buffer has a respective fixed memory capacity for storing the fetched data. The processing unit activates layers in the output image for displaying an output image on the display. The channels correspond to associated layers. The buffer controller adds to the respective fixed memory capacity of a particular buffer associated to an activated layer, one further fixed memory capacity of at least one further buffer associated to an inactive layer.
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8.发明授权公开(公告)号：US09679541B2
公开(公告)日：2017-06-13
申请号：US14707531
申请日：2015-05-08
CPC分类号： G09G5/395 , G06T15/40 , G09G5/14 , G09G5/363 , G09G2310/04 , G09G2330/021 , G09G2350/00
摘要： A display system and a method of displaying an image are hereby presented. The display system is arranged to display an image on a screen which has at least one useful screen area which is intended to be seen by a user and at least one non-useful screen area which the user cannot see. The display device comprises a bandwidth saver unit arranged to determine a location on the screen of a current pixel to be displayed. If the pixel is located in a non-useful screen area of the screen, then the fetching from a data memory of a pixel value is inhibited by the bandwidth saver unit with respect to this pixel, and a replacement, fixed pixel value is passed to a data processing unit for further processing.
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9.发明申请公开(公告)号：US20170200251A1
公开(公告)日：2017-07-13
申请号：US14992072
申请日：2016-01-11
CPC分类号： G06T1/20 , G09G5/006 , G09G5/18 , G09G5/36 , G09G5/397 , G09G2340/0435 , G09G2340/10
摘要： A display control apparatus comprising at least one display controller arranged to transmit composite pixel data to at least one display device at a rate defined by a pixel clock signal. The display control apparatus further comprises at least one pixel clock control component arranged to receive an indication of a number of graphics layers to be blended for the composite pixel data to be output, and to configure the pixel clock for the transmission of the composite pixel data to the at least one display device based at least partly on the received indication of the number of graphics layers to be blended.
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公开(公告)号：US09607583B2
公开(公告)日：2017-03-28
申请号：US14614517
申请日：2015-02-05
CPC分类号： G09G5/363 , G06F3/14 , G09G3/20 , G09G5/00 , G09G5/12 , G09G2330/12 , G09G2340/10
摘要： A display controller device for processing image data has a data processor for generating a display signal. The device has a writeback unit having an input coupled to the display signal and an output coupled to a debug interface. The writeback unit has a slice controller for defining a set of slices of the image and consecutively selecting slices of the set, and a slice selector for sampling pixel data from a selected slice. A slice buffer is coupled between the slice selector and the debug output for temporarily storing the selected pixel data. The slice controller transfers the selected pixel data to the debugger and subsequently selects a next slice until all slices of the set have been transferred. The debug system receives the slices and regenerates and displays the image.
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