公开(公告)号：US06981192B2

公开(公告)日：2005-12-27

申请号：US10256586

申请日：2002-09-27

申请人： Michael C. Panis

发明人： Michael C. Panis

IPC分类号： G01R31/319 ,  G01R31/3193 ,  G11B20/20 ,  G06F11/00

CPC分类号： G01R31/31924 ,  G01R31/31908 ,  G01R31/31937

摘要： A pin electronics circuit for automatic test equipment includes first and second sampling circuits for sampling first and second legs of a differential signal produced by a DUT (Device Under Test). Timing signals activate the first and second sampling circuits to sample the legs of the differential signal at precisely defined instants of time to produce first and second collections of samples. To deskew the legs of a differential signal with respect to each other, corresponding features within the first and second collections are identified and a difference is taken between them. The differential skew can then be applied to correct measurements of differential signals.

摘要翻译： 用于自动测试设备的引脚电子电路包括用于对DUT（被测设备）产生的差分信号的第一和第二支路进行采样的第一和第二采样电路。 定时信号激活第一和第二采样电路，以精确定义的时刻来采样差分信号的支路，以产生第一和第二采样集合。 为了相对于彼此偏移差分信号的腿，识别第一和第二集合内的对应特征，并且在它们之间取得差异。 然后可以应用差分偏移来校正差分信号的测量。

公开(公告)号：US07337377B2

公开(公告)日：2008-02-26

申请号：US11315974

申请日：2005-12-22

申请人： Michael C. Panis ,  Bradford B. Robbins

发明人： Michael C. Panis ,  Bradford B. Robbins

IPC分类号： G01R31/28

CPC分类号： G01R31/31716 ,  G01R31/3004 ,  G01R31/3016 ,  H04L1/243

摘要： A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for receiving an input serial bit stream from the device under test. The transmitter is coupled to a RX line of the device under test for providing an output serial bit stream to the device under test. The receiver is coupled to the transmitter for establishing a loopback connection. A time distortion circuit is interposed between the receiver and the transmitter, for adding predetermined amounts of timing distortion to the output serial bit stream. In addition, a selector is interposed between the receiver and the transmitter, for selecting between the receiver and a direct input. The direct input provides an algorithmic test signal that differs from the input serial bit stream received by the receiver. The direct input thus allows a tester to exercise the device under test with a test signal that differs from the signal that the device under test generates. A time measurement circuit measures timing characteristics of the device under test, and a parametric measurement circuit measures steady-state characteristics of the device under test.

摘要翻译： 用于经济地彻底测试电子设备的串行端口的系统和方法包括接收机和发射机。 接收器耦合到被测设备的TX线路，用于接收来自被测器件的输入串行比特流。 发射机耦合到被测设备的RX线路，以向被测设备提供输出串行比特流。 接收机耦合到发射机，用于建立环回连接。 时间失真电路插在接收机和发射机之间，用于将预定量的定时失真加到输出串行比特流。 此外，选择器插在接收器和发射器之间，用于在接收器和直接输入之间进行选择。 直接输入提供与接收机接收的输入串行比特流不同的算法测试信号。 因此，直接输入允许测试者使用与被测器件产生的信号不同的测试信号来锻炼被测器件。 时间测量电路测量被测器件的定时特性，参数测量电路测量被测器件的稳态特性。

公开(公告)号：US06550036B1

公开(公告)日：2003-04-15

申请号：US09409618

申请日：1999-10-01

申请人： Michael C. Panis

发明人： Michael C. Panis

IPC分类号： G06F1100

CPC分类号： G01R31/31937

摘要： A pre-conditioner for enabling high-speed time interval measurements in an ATE system having a relatively low-bandwidth pathway between a UUT and a timer/counter includes a frequency divider and a D flip-flop located near the UUT. The frequency divider receives a first input signal from the UUT and produces a first output signal having a frequency equal to 1/N times the frequency of the first input signal. The first output signal connects over the low-bandwidth pathway to a first channel of the timer/counter. The first output signal also connects to the D input of the D flip-flop. The pre-conditioner receives a second input signal from the UUT that drives the CLOCK input of the D flip-flop. The Q output of the D flip-flop supplies a second output of the pre-conditioner. The second output connects over the low-bandwidth pathway to a second channel of the timer/counter. The time interval between successive rising edges of the output signals precisely match the time interval between successive rising edges of the input signals. Although the pre-conditioner preserves the edge locations of its input signals, the frequency of the signals it sends to the timer/counter is 1/N times the input frequency. The pre-conditioner thus enables to the timer/counter to measure closely spaced, consecutive edges of inputs over a low-bandwidth path. Multiplexors, inverters, and additional frequency dividers may be included with the pre-conditioner to enhance its functionality.

摘要翻译： 在具有在UUT和定时器/计数器之间的相对低带宽路径的ATE系统中实现高速时间间隔测量的预调节器包括位于UUT附近的分频器和D触发器。 分频器从UUT接收第一输入信号，产生频率等于第一输入信号频率的1 / N倍的第一输出信号。 第一个输出信号通过低带宽通道连接到定时器/计数器的第一个通道。 第一个输出信号也连接到D触发器的D输入。 预调节器接收来自驱动D触发器的CLOCK输入的UUT的第二输入信号。 D触发器的Q输出提供预调节器的第二输出。 第二个输出端通过低带宽通道连接到定时器/计数器的第二个通道。 输出信号的连续上升沿之间的时间间隔精确地匹配输入信号的连续上升沿之间的时间间隔。 虽然预调节器保留了其输入信号的边沿位置，但它发送到定时器/计数器的信号的频率是输入频率的1 / N倍。 因此，预调节器使得定时器/计数器能够在低带宽路径上测量输入的紧密间隔的连续边缘。 预处理器可以包括多路复用器，逆变器和附加分频器以增强其功能。

公开(公告)号：US5938780A

公开(公告)日：1999-08-17

申请号：US933391

申请日：1997-09-19

申请人： Michael C. Panis

发明人： Michael C. Panis

IPC分类号： G01R31/3193 ,  G01R31/28

CPC分类号： G01R31/31935 ,  G01R31/31937

摘要： A method for operating automatic test equipment for capturing digital data produced by a semiconductor device under test, whereby the digital data is repetitively sampled to produce a series of sampled data pairs. The digital data and the sampling frequency can be non-coherent. As a result, the digital data can be sampled early relative to some bits and late relative to other bits. The sampled data pairs that are captured while these shifts take place, from early-to-late sampling or from late-to-early sampling, are then assigned to respective groups. A minimum number of bit patterns, corresponding to the sampled digital data, is then derived from contiguous groups of sampled data pairs, and compared with expected bit patterns. The method is especially useful for capturing digital data with drifting frequency.

摘要翻译： 一种用于操作用于捕获由被测半导体器件产生的数字数据的自动测试设备的方法，由此数字数据被重复采样以产生一系列采样数据对。 数字数据和采样频率可以是非相干的。 因此，数字数据可以相对于某些位提前抽取，相对于其他位来说可能较晚。 然后将从早到晚采样或从早到晚采样进行这些转换时捕获的采样数据对分配给相应的组。 然后从连续的采样数据组中得到对应于采样的数字数据的最小数量的位模式，并与预期位模式进行比较。 该方法对于捕获具有漂移频率的数字数据特别有用。

公开(公告)号：US07017087B2

公开(公告)日：2006-03-21

申请号：US09751633

申请日：2000-12-29

申请人： Michael C. Panis ,  Bradford B. Robbins

发明人： Michael C. Panis ,  Bradford B. Robbins

IPC分类号： G01R31/28

CPC分类号： G01R31/31716 ,  G01R31/3004 ,  G01R31/3016 ,  H04L1/243

摘要： A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for receiving an input serial bit stream from the device under test. The transmitter is coupled to a RX line of the device under test for providing an output serial bit stream to the device under test. The receiver is coupled to the transmitter for establishing a loopback connection. A time distortion circuit is interposed between the receiver and the transmitter, for adding predetermined amounts of timing distortion to the output serial bit stream. In addition, a selector is interposed between the receiver and the transmitter, for selecting between the receiver and a direct input. The direct input provides an algorithmic test signal that differs from the input serial bit stream received by the receiver. The direct input thus allows a tester to exercise the device under test with a test signal that differs from the signal that the device under test generates. A time measurement circuit measures timing characteristics of the device under test, and a parametric measurement circuit measures steady-state characteristics of the device under test.

公开(公告)号：US5689515A

公开(公告)日：1997-11-18

申请号：US638026

申请日：1996-04-26

申请人： Michael C. Panis

发明人： Michael C. Panis

IPC分类号： G01R31/319 ,  G01R31/28

CPC分类号： G01R31/31926 ,  G01R31/31922

摘要： A tester that produces digital timing signals having fast data rates including multiple groups of timing generators, multiple "exclusive-or" gates, and an "or" gate. Each group of timing generators is connected to an exclusive-or gate, and the output of each exclusive-or gate is coupled to the or gate. The digital timing signals are encoded such that the timing generators in each group may assert timing pulses only during specified cycles within a series of clock cycles. Each combination of timing generators within a group either asserting their respective encoded timing signals, or not asserting any timing signals during the series of clock cycles, generates a unique serial data stream. The serial data streams generated by the groups of timing generators are then combined to produce a new digital timing signal having a data rate that is faster than the data rate of the encoded digital timing signals.

摘要翻译： 产生具有快速数据速率的数字定时信号的测试器，包括多组定时发生器，多个“异或”门和“或”门。 每组定时发生器连接到异或门，并且每个异或门的输出耦合到门或门。 对数字定时信号进行编码，使得每组中的定时发生器只能在一系列时钟周期内的指定周期内断言定时脉冲。 组内的定时发生器的每个组合或者在一系列时钟周期内断言它们各自的编码定时信号，或者不断言任何定时信号，产生唯一的串行数据流。 然后将由定时发生器组产生的串行数据流组合以产生具有比编码数字定时信号的数据速率更快的数据速率的新数字定时信号。

公开(公告)号：US5604751A

公开(公告)日：1997-02-18

申请号：US555438

申请日：1995-11-09

申请人： Michael C. Panis

发明人： Michael C. Panis

IPC分类号： G01R29/02 ,  G01R31/30 ,  G01R31/319 ,  G01R31/3193 ,  G01R35/00 ,  G01R31/28

CPC分类号： G01R31/30 ,  G01R29/02 ,  G01R31/31937 ,  G01R35/00 ,  G01R31/3191

摘要： A method for automatically testing digital electronic circuits and performing time measurements whereby a digital signal having a frequency f1 is sampled at a rate equal to f2. The sampling frequency f2 is either slightly less than or slightly greater than f1. As a result, the digital signal is sampled at either a slightly later position in time or a slightly earlier position in time during each successive period of the digital signal. After the entire interval of interest on the digital signal has been sampled, either the number of logical high data samples or the number of logical low data samples is determined. Finally, the number of data samples is multiplied by the effective time period between data samples. In this way, pulse widths on digital signals can be measured with both high resolution and good linearity. This method of time measurement may also be used to calibrate an electronic circuit tester.

摘要翻译： 一种用于自动测试数字电子电路并执行时间测量的方法，由此具有频率f1的数字信号以等于f2的速率被采样。 采样频率f2略小于或稍大于f1。 结果，数字信号在数字信号的每个连续周期期间的稍后稍后的位置或稍早时间的位置中被采样。 在对数字信号的整个感兴趣间隔进行采样之后，确定逻辑高数据样本的数量或逻辑低数据样本的数量。 最后，将数据样本的数量乘以数据样本之间的有效时间段。 以这种方式，可以以高分辨率和良好的线性度测量数字信号上的脉冲宽度。 这种时间测量方法也可用于校准电子电路测试仪。