公开(公告)号：US20100220749A1

公开(公告)日：2010-09-02

申请号：US12777439

申请日：2010-05-11

申请人： Michael COLMANT ,  Alan Benner ,  Francois G. Abel ,  Michel Poret ,  Norbert Schumacher ,  Alain Blanc ,  Mark Verhappen ,  Mitch Gusat

发明人： Michael COLMANT ,  Alan Benner ,  Francois G. Abel ,  Michel Poret ,  Norbert Schumacher ,  Alain Blanc ,  Mark Verhappen ,  Mitch Gusat

IPC分类号： H04J3/06

CPC分类号： H04L49/153 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/3072 ,  H04L49/3081 ,  H04L49/45

摘要： A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

摘要翻译： 一种通信系统，由多个模块组成，在分组的分段上并行运行，以提高速度和处理能力。 一个模块作为主机，其他模块由主模块导出的控制信号控制的从模块。 重要的是，在每个模块中，数据段和每个分组的相应控制信号被正确同步，因为在大系统中，承载分组段和控制信号路径的数据路径可能具有显着不同的延迟。 本发明提供了传播延迟差的测量和用于在每个从模块中引入受控延迟，使得数据段和控制信号可以通过延迟其中一个或另一个来正确地相关。 同步数据包除正常数据包之外传输，用于获取用于确定延迟差的时间戳。

公开(公告)号：US07720105B2

公开(公告)日：2010-05-18

申请号：US10512671

申请日：2003-03-31

申请人： Michael Colmant ,  Alan Benner ,  Francois G. Abel ,  Michel Poret ,  Norbert Schumacher ,  Alain Blanc ,  Mark Verhappen ,  Mitch Gusat

发明人： Michael Colmant ,  Alan Benner ,  Francois G. Abel ,  Michel Poret ,  Norbert Schumacher ,  Alain Blanc ,  Mark Verhappen ,  Mitch Gusat

IPC分类号： H04L7/00

CPC分类号： H04L49/153 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/3072 ,  H04L49/3081 ,  H04L49/45

摘要： For switching or transmitting data packets, one can provide communication systems which consist of several modules —operating in parallel on segments of a packet —to increase speed and handling capacity. One module acts as master, others are slave modules controlled by control signals derived by the master module. It is important to correctly synchronize in each module the data segment and the respective control signal of each packet, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

摘要翻译： 对于切换或传输数据分组，可以提供由多个模块组成的通信系统，这些模块在分组的段上并行运行，以提高速度和处理能力。 一个模块作为主机，另一个模块是由主模块导出的控制信号控制的从模块。 在每个模块中正确同步数据段和每个数据包的相应控制信号是很重要的，因为在大型系统中，携带数据包的数据路径和控制信号路径可能具有显着不同的延迟。 本发明提供了传播延迟差的测量和用于在每个从模块中引入受控延迟，使得数据段和控制信号可以通过延迟其中一个或另一个来正确地相关。 同步数据包除正常数据包之外传输，用于获取用于确定延迟差的时间戳。

公开(公告)号：US08009702B2

公开(公告)日：2011-08-30

申请号：US12777439

申请日：2010-05-11

申请人： Michel Colmant ,  Alan Benner ,  Francois G. Abel ,  Michel Poret ,  Norbert Schumacher ,  Alain Blanc ,  Mark Verhappen ,  Mitch Gusat

发明人： Michel Colmant ,  Alan Benner ,  Francois G. Abel ,  Michel Poret ,  Norbert Schumacher ,  Alain Blanc ,  Mark Verhappen ,  Mitch Gusat

IPC分类号： H04J3/06

CPC分类号： H04L49/153 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/3072 ,  H04L49/3081 ,  H04L49/45

摘要： A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

摘要翻译： 一种通信系统，由多个模块组成，在分组的分段上并行运行，以提高速度和处理能力。 一个模块作为主机，其他模块由主模块导出的控制信号控制的从模块。 重要的是，在每个模块中，数据段和每个分组的相应控制信号被正确同步，因为在大系统中，承载分组段和控制信号路径的数据路径可能具有显着不同的延迟。 本发明提供了传播延迟差的测量和用于在每个从模块中引入受控延迟，使得数据段和控制信号可以通过延迟其中一个或另一个来正确地相关。 同步数据包除正常数据包之外传输，用于获取用于确定延迟差的时间戳。

公开(公告)号：US20060251124A1

公开(公告)日：2006-11-09

申请号：US10512671

申请日：2003-03-31

申请人： Michel Colmant ,  Alan Benner ,  Francois Abel ,  Michel Poret ,  Norhert Schumacher ,  Alain Blanc ,  Mark Verhappen ,  Mitch Gusat

发明人： Michel Colmant ,  Alan Benner ,  Francois Abel ,  Michel Poret ,  Norhert Schumacher ,  Alain Blanc ,  Mark Verhappen ,  Mitch Gusat

IPC分类号： H04J3/06

CPC分类号： H04L49/153 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/3072 ,  H04L49/3081 ,  H04L49/45

摘要： For switching or transmitting data packets, one can provide communication systems which consist of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master (21), the others are slave modules (22) controlled by control signals (25) derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

摘要翻译： 对于切换或传输数据分组，可以提供由多个模块组成的通信系统 - 在分组的分段上并行操作 - 以提高速度和处理能力。 一个模块作为主机（21），其他模块是由主模块导出的控制信号（25）控制的从模块（22）。 重要的是，在每个模块中，数据段和每个分组的相应控制信号被正确同步，因为在大系统中，承载分组段和控制信号路径的数据路径可能具有显着不同的延迟。 本发明提供了传播延迟差的测量和用于在每个从模块中引入受控延迟，使得数据段和控制信号可以通过延迟其中一个或另一个来正确地相关。 同步数据包除正常数据包之外传输，用于获取用于确定延迟差的时间戳。

公开(公告)号：US08085789B2

公开(公告)日：2011-12-27

申请号：US12365091

申请日：2009-02-03

申请人： Alain Blanc ,  Rene Glaise ,  Francois Le Maut ,  Michel Poret

发明人： Alain Blanc ,  Rene Glaise ,  Francois Le Maut ,  Michel Poret

IPC分类号： H04L12/28

CPC分类号： H04L49/3027 ,  H04L49/103 ,  H04L49/201 ,  H04L49/3045

摘要： A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism is disclosed. An egress location for an ingress port is selected based on degrees of freedom for the selection mechanism. The degree of freedom can be derived from the collapsed virtual output queuing array by determining a number of egress locations to which an ingress port may send packets and determining a number of ingress ports from which an egress location can receive packets. Analyzing all the queued packets for assignment to an egress location, starting with a lesser degree of freedom and ending with a greater degree of freedom provides efficient switching allocations and acknowledgements.

摘要翻译： 公开了一种使用请求/确认机制来选择在折叠的虚拟输出排队阵列（cVOQ）切换核心中切换的分组的方法。 基于选择机制的自由度选择入口端口的出口位置。 可以通过确定进入端口可以发送分组的出口位置的数量并确定出口位置可以从哪个入口端口接收分组的数目的入口端口，从折叠的虚拟输出排队阵列导出自由度。 分析所有排队的分组以分配到出口位置，以较小的自由度开始，并以更大的自由度结束，从而提供有效的切换分配和确认。

公开(公告)号：US07430167B2

公开(公告)日：2008-09-30

申请号：US10711320

申请日：2004-09-10

申请人： Rene Glaise ,  Alain Blanc ,  Francois Le Maut ,  Michel Poret

发明人： Rene Glaise ,  Alain Blanc ,  Francois Le Maut ,  Michel Poret

IPC分类号： G06F11/00

CPC分类号： H04L47/125 ,  H04L49/1523 ,  H04L49/25 ,  H04L49/30 ,  H04L49/3045

摘要： A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g., for replacing the defective individual switching plane or device.

摘要翻译： 基于在入口端口适配器和折叠虚拟输出队列（cVOQ）阵列之间交换的请求和确认的监视来适应并行分组交换机（PPS）的平面上的入局业务的负载平衡的方法和系统， 位于平面开关芯内。 根据本发明，至少一个计数器在每个入口端口适配器中被关联到要监视的每个单独的切换平面或设备。 当将请求发送到相应的单独的交换平面或设备时，这些计数器中的每一个递增，并且当从该单独的交换平面或设备接收到确认时递减。 当相同入口端口适配器的计数器所取值的范围达到预定阈值时，较少（或无））进入流量进一步传输到与较高值计数器相关联的单独交换平面或设备。 也可能引起报警信号，例如用于更换有缺陷的单独开关平面或装置。

公开(公告)号：US07769003B2

公开(公告)日：2010-08-03

申请号：US11852661

申请日：2007-09-10

申请人： Rene Glaise ,  Alain Blanc ,  Francois Le Maut ,  Michel Poret

发明人： Rene Glaise ,  Alain Blanc ,  Francois Le Maut ,  Michel Poret

IPC分类号： H04L12/50 ,  H04Q11/00 ,  H04L12/28 ,  H04L12/56

CPC分类号： H04L49/15 ,  H04L49/103 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/253 ,  H04L49/90

摘要： A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.

摘要翻译： 包括输入和输出端口的高速数据分组交换机以及将每个输入端口链接到每个输出端口的交换结构，其中输入和输出端口之间的每个连接包括动态缓冲存储器，用于存储至少一个数据分组用于最小指定的存储时间 被披露。 当通过输入端口接收到数据包时，它被写入连接到该输入端口的所有单独的动态存储器缓冲器中，以便具有输入数据包的副本准备通过任何输出端口来支持单播，多播和广播 交通。 给定数据包交换机的架构及其控制算法，动态内存缓冲区既不需要刷新，也不需要在读取后恢复其内容。

公开(公告)号：US07706394B2

公开(公告)日：2010-04-27

申请号：US10894582

申请日：2004-07-20

申请人： Alain Blanc ,  Rene Glaise ,  Francois Le Maut ,  Michel Poret

发明人： Alain Blanc ,  Rene Glaise ,  Francois Le Maut ,  Michel Poret

IPC分类号： H04L12/28 ,  H04L12/54

CPC分类号： H04L47/10 ,  H04L47/263 ,  H04L47/30 ,  H04L49/103 ,  H04L49/3027 ,  H04L49/3045

摘要： A system and a method to avoid packet traffic congestion in a shared-memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers, is disclosed. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the shared-memory switch core only if the switch core can actually forward it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion. Furthermore, since a packet is admitted in the switch core only if it can be transmitted to the corresponding egress buffer, the shared memory is reduced.

摘要翻译： 公开了一种在共享存储器交换机核心中避免分组业务拥塞的系统和方法，同时显着地减少了交换机核心和相关联的出口缓冲器中的共享存储器的数量。 根据本发明，分组交换结构的所有入口适配器的虚拟输出排队（VOQ）被折叠到其中央交换机核心中以允许有效的流控制。 数据包从入口缓冲区传输到交换机核心受到请求/确认的机制。 因此，只有当交换机核心才能将其转发到相应的出口缓冲区时，才将数据包从虚拟输出队列传输到共享存储交换机内核。 基于令牌的机制允许交换机核心确定出口缓冲区的占用水平。 因此，由于交换机核心知道输入和输出适配器的状态，因此能够优化分组交换并避免分组拥塞。 此外，由于分组只有在可以发送到对应的出口缓冲器的情况下才允许在交换机核心中，所以共享存储器被减少。

公开(公告)号：US07403536B2

公开(公告)日：2008-07-22

申请号：US10722901

申请日：2003-11-26

申请人： Alain Blanc ,  Rene Glaise ,  Michel Poret ,  Daniel Wind

发明人： Alain Blanc ,  Rene Glaise ,  Michel Poret ,  Daniel Wind

IPC分类号： H04L12/56

CPC分类号： H04L49/153 ,  H04L12/5601 ,  H04L49/1523 ,  H04L49/30 ,  H04L49/3045 ,  H04L49/3081 ,  H04L49/50 ,  H04L2012/565 ,  H04L2012/5679 ,  H04L2012/568

摘要： A method to resequence packets includes sequentially allocating in each source ingress adapter a packet rank to each packet received within each source ingress adapter. In each destination egress adapter, each ranked data packet is stored at a respective buffer address of an egress buffer. The respective buffer addresses of data packets received by a same source ingress adapter with a same priority level and switched through a same switching plane are linked in a same linked-list. The respective buffer addresses are preferably linked by their order of use in the egress buffer, and thus each linked-list is having a head list pointing to the oldest buffer address. The linked-lists are sorted into subsets including those linked-lists linking the respective buffer addresses of data packets received by a same source ingress adapter with a same priority level. For each subset of linked-lists, the packet ranks of the data packets stored at the buffer address pointed by the head lists of each linked-list of each subset are compared to determine the next data packet to be put in a sequence.

摘要翻译： 重新分配分组的方法包括在每个源入口适配器中顺序分配每个源入口适配器中接收的每个分组的分组等级。 在每个目的地出口适配器中，每个排序的数据分组被存储在出口缓冲器的相应缓冲器地址处。 具有相同优先级的相同源入口适配器接收的并通过相同交换平面切换的数据分组的相应缓冲器地址被链接在相同的链表中。 相应的缓冲器地址优选地通过它们在出口缓冲器中的使用顺序来链接，因此每个链表都具有指向最旧缓冲器地址的头列表。 链接列表被分类为包括链接列表的链接列表，其链接相同的源入口适配器接收的数据分组的相应缓冲器地址具有相同的优先级。 对于链接列表的每个子集，比较存储在由每个子集的每个链表的头列表指向的缓冲地址处的数据分组的分组等级以确定要放入序列的下一个数据分组。

公开(公告)号：US20080013548A1

公开(公告)日：2008-01-17

申请号：US11852661

申请日：2007-09-10

申请人： Rene Glaise ,  Alain Blanc ,  Francois Maut ,  Michel Poret

发明人： Rene Glaise ,  Alain Blanc ,  Francois Maut ,  Michel Poret

IPC分类号： H04L12/56

CPC分类号： H04L49/15 ,  H04L49/103 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/253 ,  H04L49/90

摘要： A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.

摘要翻译： 包括输入和输出端口的高速数据分组交换机以及将每个输入端口链接到每个输出端口的交换结构，其中输入和输出端口之间的每个连接包括动态缓冲存储器，用于存储至少一个数据分组用于最小指定的存储时间 被披露。 当通过输入端口接收到数据包时，它被写入连接到该输入端口的所有单独的动态存储器缓冲器中，以便具有输入数据包的副本准备通过任何输出端口来支持单播，多播和广播 交通。 给定数据包交换机的架构及其控制算法，动态内存缓冲区既不需要刷新，也不需要在读取后恢复其内容。