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公开(公告)号：US07584375B2
公开(公告)日：2009-09-01
申请号：US11443141
申请日：2006-05-26
IPC分类号： G06F1/32
CPC分类号： G06F1/3209
摘要： A distributed power management system for a bus architecture or similar communications network. The system supports multiple low power states and defines entry and exit procedures for maximizing energy savings and communication speed.
摘要翻译： 用于总线架构或类似通信网络的分布式电源管理系统。 该系统支持多种低功耗状态，并定义了最大化节能和通信速度的进入和退出程序。
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公开(公告)号：US07225350B2
公开(公告)日：2007-05-29
申请号：US11443140
申请日：2006-05-26
CPC分类号： G06F1/3209
摘要： A distributed power management system for a bus architecture or similar communications network. The system supports multiple low power states and defines entry and exit procedures for maximizing energy savings and communication speed.
摘要翻译： 用于总线架构或类似通信网络的分布式电源管理系统。 该系统支持多种低功耗状态，并定义了最大化节能和通信速度的进入和退出程序。
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公开(公告)号：US07137018B2
公开(公告)日：2006-11-14
申请号：US10335111
申请日：2002-12-31
CPC分类号： G06F1/3209
摘要： A distributed power management system for a bus architecture or similar communications network. The system supports multiple low power states and defines entry and exit procedures for maximizing energy savings and communication speed.
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公开(公告)号：US07936684B2
公开(公告)日：2011-05-03
申请号：US11842280
申请日：2007-08-21
IPC分类号： H04J1/16
CPC分类号： G06F11/27 , G01R31/31716 , H04L43/50
摘要： In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，芯片包括控制电路，以提供带内信号，带内输出端口和发射器，以将带内信号传输到带内输出端口。 控制电路选择性地包括带内信号中的回送启动命令。 描述和要求保护其他实施例。
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公开(公告)号：US07464307B2
公开(公告)日：2008-12-09
申请号：US10396071
申请日：2003-03-25
申请人： Jay J. Nejedlo , Mike Wiznerowicz , David G. Ellis , Richard J. Glass , Andrew W. Martwick , Theodore Z. Schoenborn
发明人： Jay J. Nejedlo , Mike Wiznerowicz , David G. Ellis , Richard J. Glass , Andrew W. Martwick , Theodore Z. Schoenborn
CPC分类号： G01R31/3187 , G01R31/31717 , H04L1/242
摘要： According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.
摘要翻译： 根据一个实施例，公开了内置自检（IBIST）架构/方法。 IBIST提供测试发射机和接收机组件之间的互连（例如总线）的功能。 IBIST架构包括一个模式生成器和一个模式检查器。 模式检查器操作以将接收到的多个比特（对于模式生成器）与先前存储的多个比特进行比较。
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公开(公告)号：US07444558B2
公开(公告)日：2008-10-28
申请号：US10750034
申请日：2003-12-31
申请人： Suneel G. Mitbander , Cass A. Blodgett , Andrew W. Martwick , Lyonel Renaud , Theodore Z. Schoenborn
发明人： Suneel G. Mitbander , Cass A. Blodgett , Andrew W. Martwick , Lyonel Renaud , Theodore Z. Schoenborn
IPC分类号： G01R31/28
CPC分类号： G06F11/221 , G01R31/31716
摘要： A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and configure a lane transmitter for the link. A start bit in a register of the IC device is programmed, to request that the link be placed in a measurement mode. In this mode, the IC device instructs the other IC device to enter a loopback mode for the link. The IC device transmits a sequence of test symbols over the link and evaluates a loopback version of the sequence for errors. The sequence of test symbols have a data pattern, and are transmitted, as configured by the registers. Other embodiments are also described and claimed.
摘要翻译： 将集成电路（IC）设备通信耦合到另一个IC设备的串行点对点链路通过在链路上传送符号的训练序列来初始化。 对IC器件的寄存器进行编程，设置符号数据模式并为链路配置通道发送器。 对IC器件的寄存器中的起始位进行编程，要求将链路置于测量模式。 在该模式中，IC装置指示其他IC装置输入链路的环回模式。 IC设备通过链路发送测试符号序列，并评估序列的环回版本的错误。 测试符号序列具有数据模式，并由寄存器配置发送。 还描述和要求保护其他实施例。
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公开(公告)号：US07184708B1
公开(公告)日：2007-02-27
申请号：US10629967
申请日：2003-07-30
申请人： Seh W. Kwa , David Q. Xu , Alan E. Waltho , Andrew W. Martwick , Ravid Shmuel
发明人： Seh W. Kwa , David Q. Xu , Alan E. Waltho , Andrew W. Martwick , Ravid Shmuel
CPC分类号： H04B15/02 , H04B2215/067
摘要： Interference within a wireless apparatus is mitigated by adjusting one or more transmission characteristics associated with an interconnect of the apparatus. In at least one embodiment, the interconnect is a PCI Express interconnect.
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公开(公告)号：US20150188736A1
公开(公告)日：2015-07-02
申请号：US14140588
申请日：2013-12-26
IPC分类号： H04L25/08
CPC分类号： H04L25/08
摘要： A computing device can include a radio receiver to receive a radio signal from a radio transmitter of a second computing or communication device. The radio receiver can experience radio frequency interference. The computing device can also include a digital signal generator. The digital signal generator can be to process a signal (S1) underlying a source of the radio frequency interference. The digital signal generator can also be to generate a digital signal (S1). The digital signal generator can further be to inject the digital signal (S1) into the radio receiver to cancel the radio frequency interference around the radio frequency of interest.
摘要翻译： 计算设备可以包括无线电接收机，用于从第二计算或通信设备的无线电发射机接收无线电信号。 无线电接收机可能会遇到射频干扰。 计算设备还可以包括数字信号发生器。 数字信号发生器可以处理基于射频干扰源的信号（S1）。 数字信号发生器也可以产生数字信号（S1）。 数字信号发生器还可以将数字信号（S1）注入到无线电接收机中以消除感兴趣的射频周围的射频干扰。
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9.发明授权Autodetection of a PCI express device operating at a wireless RF mitigation frequency 有权自动检测以无线RF减轻频率工作的PCI Express设备公开(公告)号：US08041844B2
公开(公告)日：2011-10-18
申请号：US11026968
申请日：2004-12-29
IPC分类号： G06F3/00 , G06F13/00 , G06F5/00 , G06F1/24 , H04B3/36 , H04B7/14 , H04B1/18 , H04B1/38 , H04B3/20 , H04M1/00 , H04M11/00 , H03H7/30
CPC分类号： G06F13/4295 , G06F2213/0026 , H04L7/10
摘要： A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.
摘要翻译： 描述了检测符合PCI Express的端点设备的计算机系统。 具体地，计算机系统以第一频率对发射和接收电路进行计时，并启动训练序列。 如果端点设备成功地以第一个频率列车，则端点设备符合PCI Express标准。 否则，计算机系统以第二频率发起另一训练序列。
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10.发明申请CORRECTING DOUBLE-BIT BURST ERRORS USING A LOW DENSITY PARITY CHECK TECHNIQUE 有权使用低密度奇偶校验技术校正双位BURST错误公开(公告)号：US20110161773A1
公开(公告)日：2011-06-30
申请号：US12651323
申请日：2009-12-31
申请人： Andrew W. Martwick , Terry Fletcher
发明人： Andrew W. Martwick , Terry Fletcher
CPC分类号： G06F11/10 , H03M13/13 , H03M13/17 , H04L1/0045 , H04L1/0057
摘要： Embodiments of systems, apparatuses, and methods for correcting double bit burst errors using a low density parity check technique are disclosed. In one embodiment, an apparatus includes an encoder to generate a parity vector by multiplying a first version of a data vector by a matrix. The parity vector is to identify correctable double-bit burst errors in a second version of the data vector. The apparatus also includes logic to concatenate the parity vector and the first version of the data vector.
摘要翻译： 公开了使用低密度奇偶校验技术来校正双位突发错误的系统，装置和方法的实施例。 在一个实施例中，一种装置包括编码器，用于通过将数据向量的第一版本乘以矩阵来生成奇偶校验向量。 奇偶校验向量是识别数据向量的第二版本中的可纠正的双比特突发错误。 该装置还包括连接奇偶校验向量和数据向量的第一版本的逻辑。
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