公开(公告)号：US06534243B1

公开(公告)日：2003-03-18

申请号：US10000493

申请日：2001-10-23

申请人： Michael K. Templeton ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Kathleen R. Early ,  Ursula Q. Quinto

发明人： Michael K. Templeton ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Kathleen R. Early ,  Ursula Q. Quinto

IPC分类号： G03F7039

CPC分类号： G03F7/405 ,  G03F7/0035 ,  G03F7/40

摘要： In one embodiment, the present invention relates to a method of treating a patterned resist involving providing the patterned resist having a first number of structural features, the patterned resist comprising an acid catalyzed polymer; contacting a coating containing a coating material, at least one basic compound, a photoacid generator, and a dye with the patterned resist; irradiating the coated patterned resist; permitting a deprotection region to form within an inner portion of the patterned resist; and removing the coating and the deprotection region to provide a second number of patterned resist structural features, wherein the first number is smaller than the second number.

摘要翻译： 在一个实施方案中，本发明涉及一种处理图案化抗蚀剂的方法，包括提供具有第一数目的结构特征的图案化抗蚀剂，所述图案化抗蚀剂包含酸催化聚合物; 使含有涂层材料的涂层，至少一种碱性化合物，光致酸发生剂和染料与图案化的抗蚀剂接触; 照射经涂覆的图案化抗蚀剂; 允许在图案化抗蚀剂的内部部分内形成去保护区; 并且去除涂层和去保护区域以提供第二数量的图案化抗蚀剂结构特征，其中第一数目小于第二数量。

公开(公告)号：US07153364B1

公开(公告)日：2006-12-26

申请号：US10000208

申请日：2001-10-23

申请人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Ursula Q. Quinto ,  Michael K. Templeton

发明人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Ursula Q. Quinto ,  Michael K. Templeton

IPC分类号： B05B1/28 ,  B05B15/04 ,  B05B3/00

CPC分类号： H01L21/6715 ,  B05B15/50 ,  B05C11/08

摘要： The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.

摘要翻译： 本发明提供了一种用于分配头的虚拟分配抗蚀剂的系统和方法，同时减轻与虚拟分配过程相关的废物。 虚拟分配的抗蚀剂返回到被采集的储存器。 在基板应用之间，分配头可以被定位成将抗蚀剂分配到返回线中。 来自分配头的抗蚀剂的流动在分配头保持抗干燥。 通过将虚拟分配的抗蚀剂漏出到具有低体积的返回管线中，例如，可以减轻来自虚拟分配过程的废物。

公开(公告)号：US06274289B1

公开(公告)日：2001-08-14

申请号：US09708104

申请日：2000-11-06

申请人： Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan ,  Ursula Q. Quinto

发明人： Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan ,  Ursula Q. Quinto

IPC分类号： G03F711

CPC分类号： G03F7/168 ,  G03F7/40

摘要： In one embodiment, the present invention relates to a method of treating a resist layer involving the steps of providing the resist layer having a first thickness, the resist layer comprising a polymer having a labile group; contacting a coating containing at least one cleaving compound with the resist layer to form a deprotected resist layer at an interface between the resist layer and the coating; and removing the coating and the deprotected resist layer leaving a resist having a second thickness, wherein the second thickness is smaller than the first thickness.

摘要翻译： 在一个实施方案中，本发明涉及一种处理抗蚀剂层的方法，包括以下步骤：提供具有第一厚度的抗蚀剂层，抗蚀剂层包含具有不稳定基团的聚合物; 使含有至少一种裂解化合物的涂层与抗蚀剂层接触，以在抗蚀剂层和涂层之间的界面处形成去保护的抗蚀剂层; 以及去除涂层和去保护的抗蚀剂层，留下具有第二厚度的抗蚀剂，其中第二厚度小于第一厚度。

公开(公告)号：US06269322B1

公开(公告)日：2001-07-31

申请号：US09266361

申请日：1999-03-11

申请人： Michael K. Templeton ,  Bharath Rangarajan ,  Kathleen R. Early ,  Terry Manchester

发明人： Michael K. Templeton ,  Bharath Rangarajan ,  Kathleen R. Early ,  Terry Manchester

IPC分类号： G03B2742

CPC分类号： G03F9/70

摘要： The present invention relates to wafer alignment. A reticle is employed which includes, a design and first and second alignment marks. The second alignment mark is symmetric to the first alignment mark such that a reticle center point is a midpoint of the first and second alignment marks. The first alignment mark is printed on a surface layer of the wafer. The second alignment mark is printed on the surface layer at an offset from the first alignment mark. A virtual alignment mark is determined, the virtual alignment mark being a midpoint of the printed first and second alignment marks. The virtual alignment mark is employed to facilitate aligning the wafer. The symmetric relationship between the first and second alignment mark results in the negation of print errors of the marks due to reticle rotation and/or lens magnification with respect to the virtual alignment mark. The employment of the virtual alignment mark in wafer alignment substantially facilitates mitigation of overlay error.

摘要翻译： 本发明涉及晶圆对准。 使用掩模版，其包括设计和第一和第二对准标记。 第二对准标记与第一对准标记对称，使得标线片中心点是第一和第二对准标记的中点。 将第一对准标记印刷在晶片的表面层上。 第二对准标记以与第一对准标记偏移的方式印刷在表面层上。 确定虚拟对准标记，虚拟对准标记是打印的第一和第二对准标记的中点。 采用虚拟对准标记以便于对准晶片。 第一和第二对准标记之间的对称关系导致相对于虚拟对准标记由于标线旋转和/或透镜放大而导致的标记的打印错误的否定。 在晶片对准中使用虚拟对准标记基本上有助于减轻重叠误差。

公开(公告)号：US06197455B1

公开(公告)日：2001-03-06

申请号：US09231679

申请日：1999-01-14

申请人： Sanjay K. Yedur ,  Bharath Rangarajan ,  Bhanwar Singh ,  Michael K. Templeton ,  Kathleen R. Early

发明人： Sanjay K. Yedur ,  Bharath Rangarajan ,  Bhanwar Singh ,  Michael K. Templeton ,  Kathleen R. Early

IPC分类号： G03F900

CPC分类号： G03F1/74 ,  Y10S977/856 ,  Y10S977/859

摘要： A method of repairing defects in a photomask used in the formation of a semiconductor wafer includes the use of a scanning tunneling microscope. The scanning tunneling microscope includes a very sharp tip having a diameter on the order of 100 Å or less. In order to remove excess material from a mask layer in the photomask, the tip is placed into contact with those regions having such excess material and the tip is used to scrape the excess material away. In order to add material to voids in a mask layer of the photomask, the tip is placed in proximity to those areas in need of the excess material and caused to deposit such material upon, for example, application of a bias voltage to the tip.

摘要翻译： 修复用于形成半导体晶片的光掩模中的缺陷的方法包括使用扫描隧道显微镜。 扫描隧道显微镜包括具有大约等于或小于100埃的直径的非常锋利的尖端。 为了从光掩模中的掩模层去除多余的材料，将尖端放置成与具有这种多余材料的那些区域接触，并且尖端用于刮除多余的材料。 为了向光掩模的掩模层中的空隙添加材料，将尖端放置在需要多余材料的那些区域附近，并且使得将这种材料沉积在例如向尖端施加偏置电压。

公开(公告)号：US07078348B1

公开(公告)日：2006-07-18

申请号：US09893188

申请日：2001-06-27

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton

IPC分类号： H01L21/302 ,  H01L21/3065

CPC分类号： H01L21/31144 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813

摘要： One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.

摘要翻译： 本发明的一个方面涉及在单一蚀刻工艺中在绝缘层中制造双镶嵌图案的方法，该方法包括提供其上形成有至少一个绝缘层的晶片; 在所述至少一个绝缘层上沉积第一光致抗蚀剂层; 将第一图像图案化成第一光致抗蚀剂层; 固化第一图案化光致抗蚀剂层; 在所述第一图案化光致抗蚀剂层上沉积第二光致抗蚀剂层; 将第二图像图案化成第二光致抗蚀剂层; 以及在单次蚀刻工艺中同时蚀刻通过第一图案化光致抗蚀剂层和第二图案化光致抗蚀剂层的至少一个绝缘层。

公开(公告)号：US06629786B1

公开(公告)日：2003-10-07

申请号：US09845232

申请日：2001-04-30

申请人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： G03D500

CPC分类号： G03D5/00

摘要： A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.

摘要翻译： 提供了一种用于调节开发过程的时间和温度的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上显影的一个或多个光栅。 从光栅反射的光被测量系统收集，该系统处理收集的光。 通过光栅的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的显影进展。 该测量系统提供开发相关数据的进展到处理器，该处理器确定晶片的相应部分的开发进度。 该系统还包括多个加热装置，每个加热装置对应于显影剂的相应部分并提供其加热。 处理器选择性地控制加热装置，以调节晶片各部分的温度。

公开(公告)号：US06524944B1

公开(公告)日：2003-02-25

申请号：US09617374

申请日：2000-07-17

申请人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Michael K. Templeton

发明人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Michael K. Templeton

IPC分类号： H01L214763

CPC分类号： H01L21/7682

摘要： One aspect of the present invention relates to a method of forming an advanced low k material between metal lines on a semiconductor substrate, involving the steps of providing the semiconductor substrate having a plurality of metal lines thereon; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; and at least one of heating or etching the semiconductor substrate whereby at least a portion of the spin-on material is removed, thereby forming the advanced low k material comprising at least one air void between the metal lines, the advanced low k material having a dielectric constant of about 2 or less. Another aspect of the present invention relates to a method of forming a semiconductor structure, involving the steps of forming a first plurality of metal lines on the semiconductor structure; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; forming a plurality of openings in the spin-on material exposing a portion of the metal lines and depositing metal to form a plurality of metal vias in the openings; forming a second plurality of metal lines over at least a portion of the metal vias; and at least one of heating or etching the semiconductor structure whereby at least a portion of the spin-on material is removed, thereby forming an advanced low k material comprising at least one air void, the advanced low k material having a dielectric constant of about 2 or less.

摘要翻译： 本发明的一个方面涉及一种在半导体衬底上的金属线之间形成高级低k材料的方法，包括提供其上具有多条金属线的半导体衬底的步骤; 在其上具有多条金属线的半导体衬底上沉积旋涂材料; 以及加热或蚀刻半导体衬底中的至少一个，由此除去旋涂材料的至少一部分，从而形成包括金属线之间的至少一个空气空隙的高级低k材料，先进的低k材料具有 介电常数约为2或更小。 本发明的另一方面涉及一种形成半导体结构的方法，包括在半导体结构上形成第一多个金属线的步骤; 在其上具有多条金属线的半导体衬底上沉积旋涂材料; 在所述旋涂材料中形成暴露金属线的一部分并沉积金属以在所述开口中形成多个金属通孔的多个开口; 在所述金属通孔的至少一部分上形成第二多个金属线; 以及加热或蚀刻半导体结构中的至少一个，由此除去旋涂材料的至少一部分，从而形成包括至少一个空气空隙的先进的低k材料，该介电常数为约 2以下。

公开(公告)号：US06444381B1

公开(公告)日：2002-09-03

申请号：US09729295

申请日：2000-12-04

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan ,  Khoi A. Phan ,  Bryan K. Choo ,  Sanjay K. Yedur

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan ,  Khoi A. Phan ,  Bryan K. Choo ,  Sanjay K. Yedur

IPC分类号： G03F900

CPC分类号： G03F1/74 ,  Y10S430/143

摘要： One aspect of the present invention relates to a method for reducing carbon contamination on a mask involving placing a mask plate having carbon-containing contaminants thereon in a processing chamber; simultaneously contacting the mask plate with oxygen and exposing the mask plate with a flood exposure of electron beams wherein the carbon-containing contaminants are converted to a by-product; and removing the by-product from the processing chamber.

摘要翻译： 本发明的一个方面涉及一种用于减少掩模上的碳污染的方法，其涉及将具有含碳污染物的掩模板放置在处理室中; 同时使掩模板与氧气接触，并将电子束的暴露暴露于掩模板，其中含碳污染物转化为副产物; 并从处理室中除去副产物。

公开(公告)号：US06335152B1

公开(公告)日：2002-01-01

申请号：US09564408

申请日：2000-05-01

申请人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

发明人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

IPC分类号： G03F738

CPC分类号： G03F7/38

摘要： In one embodiment, the present invention relates to a method of processing an irradiated photoresist involving the steps of placing a substrate having the irradiated photoresist thereon at a first temperature in a rapid thermal anneal furnace; heating the substrate having the irradiated photoresist thereon to a second temperature within about 0.1 seconds to about 10 seconds; cooling the substrate having the irradiated photoresist thereon to a third temperature in a rapid thermal annealing furnace within about 0.1 seconds to about 10 seconds; and developing the irradiated photoresist, wherein the second temperature is higher than the first temperature and the third temperature. In another embodiment, the present invention relates to a system of processing a photoresist, containing a source of actinic radiation and a mask for selectively irradiating a photoresist; a rapid thermal annealing furnace for rapidly heating and rapidly cooling a selectively irradiated photoresist, wherein the rapid heating and rapid cooling are independently conducted within about 0.1 seconds to about 10 seconds; and a developer for developing a rapid thermal annealing furnace heated and selectively irradiated photoresist into a patterned photoresist.

摘要翻译： 在一个实施方案中，本发明涉及一种处理被照射的光致抗蚀剂的方法，包括以下步骤：在快速热退火炉中将具有照射光致抗蚀剂的基底在第一温度下放置; 将其上具有照射的光致抗蚀剂的基板加热至约0.1秒至约10秒的第二温度; 将快速热退火炉中具有照射光致抗蚀剂的基板冷却至约0.1秒至约10秒的第三温度; 并且显影所述被照射的光致抗蚀剂，其中所述第二温度高于所述第一温度和所述第三温度。 在另一个实施方案中，本发明涉及一种处理含有光化辐射源的光致抗蚀剂的系统和用于选择性地照射光致抗蚀剂的掩模; 快速热退火炉，用于快速加热和快速冷却选择性照射的光致抗蚀剂，其中快速加热和快速冷却在约0.1秒至约10秒内独立进行; 以及用于将快速热退火炉加热并选择性地照射光致抗蚀剂的显影剂加工成图案化的光致抗蚀剂。