Re-circulation and reuse of dummy-dispensed resist
    1.
    发明授权
    Re-circulation and reuse of dummy-dispensed resist 失效
    虚拟分配抗蚀剂的再循环和再利用

    公开(公告)号:US07153364B1

    公开(公告)日:2006-12-26

    申请号:US10000208

    申请日:2001-10-23

    IPC分类号: B05B1/28 B05B15/04 B05B3/00

    摘要: The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.

    摘要翻译: 本发明提供了一种用于分配头的虚拟分配抗蚀剂的系统和方法,同时减轻与虚拟分配过程相关的废物。 虚拟分配的抗蚀剂返回到被采集的储存器。 在基板应用之间,分配头可以被定位成将抗蚀剂分配到返回线中。 来自分配头的抗蚀剂的流动在分配头保持抗干燥。 通过将虚拟分配的抗蚀剂漏出到具有低体积的返回管线中,例如,可以减轻来自虚拟分配过程的废物。

    Dual layer patterning scheme to make dual damascene
    2.
    发明授权
    Dual layer patterning scheme to make dual damascene 失效
    双层图案方案制作双镶嵌

    公开(公告)号:US07078348B1

    公开(公告)日:2006-07-18

    申请号:US09893188

    申请日:2001-06-27

    IPC分类号: H01L21/302 H01L21/3065

    摘要: One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.

    摘要翻译: 本发明的一个方面涉及在单一蚀刻工艺中在绝缘层中制造双镶嵌图案的方法,该方法包括提供其上形成有至少一个绝缘层的晶片; 在所述至少一个绝缘层上沉积第一光致抗蚀剂层; 将第一图像图案化成第一光致抗蚀剂层; 固化第一图案化光致抗蚀剂层; 在所述第一图案化光致抗蚀剂层上沉积第二光致抗蚀剂层; 将第二图像图案化成第二光致抗蚀剂层; 以及在单次蚀刻工艺中同时蚀刻通过第一图案化光致抗蚀剂层和第二图案化光致抗蚀剂层的至少一个绝缘层。

    Active control of developer time and temperature
    3.
    发明授权
    Active control of developer time and temperature 失效
    主动控制显影时间和温度

    公开(公告)号:US06629786B1

    公开(公告)日:2003-10-07

    申请号:US09845232

    申请日:2001-04-30

    IPC分类号: G03D500

    CPC分类号: G03D5/00

    摘要: A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.

    摘要翻译: 提供了一种用于调节开发过程的时间和温度的系统。 该系统包括一个或多个光源,每个光源将光引导到在晶片上显影的一个或多个光栅。 从光栅反射的光被测量系统收集,该系统处理收集的光。 通过光栅的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的显影进展。 该测量系统提供开发相关数据的进展到处理器,该处理器确定晶片的相应部分的开发进度。 该系统还包括多个加热装置,每个加热装置对应于显影剂的相应部分并提供其加热。 处理器选择性地控制加热装置,以调节晶片各部分的温度。

    Low k ILD process by removable ILD
    4.
    发明授权
    Low k ILD process by removable ILD 失效
    通过可移除ILD的低k ILD过程

    公开(公告)号:US06524944B1

    公开(公告)日:2003-02-25

    申请号:US09617374

    申请日:2000-07-17

    IPC分类号: H01L214763

    CPC分类号: H01L21/7682

    摘要: One aspect of the present invention relates to a method of forming an advanced low k material between metal lines on a semiconductor substrate, involving the steps of providing the semiconductor substrate having a plurality of metal lines thereon; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; and at least one of heating or etching the semiconductor substrate whereby at least a portion of the spin-on material is removed, thereby forming the advanced low k material comprising at least one air void between the metal lines, the advanced low k material having a dielectric constant of about 2 or less. Another aspect of the present invention relates to a method of forming a semiconductor structure, involving the steps of forming a first plurality of metal lines on the semiconductor structure; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; forming a plurality of openings in the spin-on material exposing a portion of the metal lines and depositing metal to form a plurality of metal vias in the openings; forming a second plurality of metal lines over at least a portion of the metal vias; and at least one of heating or etching the semiconductor structure whereby at least a portion of the spin-on material is removed, thereby forming an advanced low k material comprising at least one air void, the advanced low k material having a dielectric constant of about 2 or less.

    摘要翻译: 本发明的一个方面涉及一种在半导体衬底上的金属线之间形成高级低k材料的方法,包括提供其上具有多条金属线的半导体衬底的步骤; 在其上具有多条金属线的半导体衬底上沉积旋涂材料; 以及加热或蚀刻半导体衬底中的至少一个,由此除去旋涂材料的至少一部分,从而形成包括金属线之间的至少一个空气空隙的高级低k材料,先进的低k材料具有 介电常数约为2或更小。 本发明的另一方面涉及一种形成半导体结构的方法,包括在半导体结构上形成第一多个金属线的步骤; 在其上具有多条金属线的半导体衬底上沉积旋涂材料; 在所述旋涂材料中形成暴露金属线的一部分并沉积金属以在所述开口中形成多个金属通孔的多个开口; 在所述金属通孔的至少一部分上形成第二多个金属线; 以及加热或蚀刻半导体结构中的至少一个,由此除去旋涂材料的至少一部分,从而形成包括至少一个空气空隙的先进的低k材料,该介电常数为约 2以下。

    Use of RTA furnace for photoresist baking
    6.
    发明授权
    Use of RTA furnace for photoresist baking 有权
    使用RTA炉进行光刻胶烘烤

    公开(公告)号:US06335152B1

    公开(公告)日:2002-01-01

    申请号:US09564408

    申请日:2000-05-01

    IPC分类号: G03F738

    CPC分类号: G03F7/38

    摘要: In one embodiment, the present invention relates to a method of processing an irradiated photoresist involving the steps of placing a substrate having the irradiated photoresist thereon at a first temperature in a rapid thermal anneal furnace; heating the substrate having the irradiated photoresist thereon to a second temperature within about 0.1 seconds to about 10 seconds; cooling the substrate having the irradiated photoresist thereon to a third temperature in a rapid thermal annealing furnace within about 0.1 seconds to about 10 seconds; and developing the irradiated photoresist, wherein the second temperature is higher than the first temperature and the third temperature. In another embodiment, the present invention relates to a system of processing a photoresist, containing a source of actinic radiation and a mask for selectively irradiating a photoresist; a rapid thermal annealing furnace for rapidly heating and rapidly cooling a selectively irradiated photoresist, wherein the rapid heating and rapid cooling are independently conducted within about 0.1 seconds to about 10 seconds; and a developer for developing a rapid thermal annealing furnace heated and selectively irradiated photoresist into a patterned photoresist.

    摘要翻译: 在一个实施方案中,本发明涉及一种处理被照射的光致抗蚀剂的方法,包括以下步骤:在快速热退火炉中将具有照射光致抗蚀剂的基底在第一温度下放置; 将其上具有照射的光致抗蚀剂的基板加热至约0.1秒至约10秒的第二温度; 将快速热退火炉中具有照射光致抗蚀剂的基板冷却至约0.1秒至约10秒的第三温度; 并且显影所述被照射的光致抗蚀剂,其中所述第二温度高于所述第一温度和所述第三温度。 在另一个实施方案中,本发明涉及一种处理含有光化辐射源的光致抗蚀剂的系统和用于选择性地照射光致抗蚀剂的掩模; 快速热退火炉,用于快速加热和快速冷却选择性照射的光致抗蚀剂,其中快速加热和快速冷却在约0.1秒至约10秒内独立进行; 以及用于将快速热退火炉加热并选择性地照射光致抗蚀剂的显影剂加工成图案化的光致抗蚀剂。

    Inverse resist coating process
    7.
    发明授权
    Inverse resist coating process 有权
    抗反射涂层工艺

    公开(公告)号:US07943289B2

    公开(公告)日:2011-05-17

    申请号:US11087011

    申请日:2005-03-22

    IPC分类号: G03F7/20

    摘要: The invention provides systems and processes that form the inverse (photographic negative) of a patterned first coating. The patterned first coating is usually provided by a resist. After the first coating is patterned, a coating of a second material is provided thereover. The uppermost layer of the second coating is removed, where appropriate, to expose the patterned first coating. The patterned first coating is subsequently removed, leaving the second coating material in the form of a pattern that is the inverse pattern of the first coating pattern. The process may be repeated with a third coating material to reproduce the pattern of the first coating in a different material. Prior to applying the second coating, the patterned first coating may be trimmed by etching, thereby reducing the feature size and producing sublithographic features. In addition to providing sublithographic features, the invention gives a simple, efficient, and high fidelity method of obtaining inverse coating patterns.

    摘要翻译: 本发明提供了形成图案化的第一涂层的逆(照相负)的系统和工艺。 图案化的第一涂层通常由抗蚀剂提供。 在对第一涂层进行图案化之后,在其上提供第二材料的涂层。 在适当的情况下去除第二涂层的最上层以暴露图案化的第一涂层。 随后去除图案化的第一涂层,留下作为第一涂层图案的相反图案的图案形式的第二涂层材料。 可以用第三涂层材料重复该过程,以以不同的材料再现第一涂层的图案。 在施加第二涂层之前,可以通过蚀刻修整图案化的第一涂层,从而减小特征尺寸并产生亚光刻特征。 除了提供亚光刻特征之外,本发明还提供了一种简单,有效和高保真的获得反涂层图案的方法。

    Chemical trim process
    9.
    发明授权
    Chemical trim process 失效
    化学修剪过程

    公开(公告)号:US06492075B1

    公开(公告)日:2002-12-10

    申请号:US09881993

    申请日:2001-06-15

    IPC分类号: G03H900

    CPC分类号: G03F7/40 G03F7/405

    摘要: In one embodiment, the present invention relates to a method of treating a patterned resist involving the steps of providing the patterned resist having structural features of a first size, the patterned resist containing a polymer having a labile group; contacting a coating containing at least one cleaving compound with the patterned resist to form a thin deprotected resist layer at an interface between the patterned resist and the coating; and removing the coating and the thin deprotected resist layer leaving the patterned resist having structural features of a second size, wherein the second size is smaller than the first size.

    摘要翻译: 在一个实施方案中,本发明涉及一种处理图案化抗蚀剂的方法,包括以下步骤:提供具有第一尺寸结构特征的图案化抗蚀剂,所述图案化抗蚀剂含有具有不稳定基团的聚合物; 使含有至少一种裂解化合物的涂层与图案化的抗蚀剂接触以在图案化的抗蚀剂和涂层之间的界面处形成薄的去保护的抗蚀剂层; 以及去除涂层和薄的去保护的抗蚀剂层,留下具有第二尺寸的结构特征的图案化抗蚀剂,其中第二尺寸小于第一尺寸。

    Chemical resist thickness reduction process
    10.
    发明授权
    Chemical resist thickness reduction process 有权
    化学抗蚀剂厚度降低过程

    公开(公告)号:US06274289B1

    公开(公告)日:2001-08-14

    申请号:US09708104

    申请日:2000-11-06

    IPC分类号: G03F711

    CPC分类号: G03F7/168 G03F7/40

    摘要: In one embodiment, the present invention relates to a method of treating a resist layer involving the steps of providing the resist layer having a first thickness, the resist layer comprising a polymer having a labile group; contacting a coating containing at least one cleaving compound with the resist layer to form a deprotected resist layer at an interface between the resist layer and the coating; and removing the coating and the deprotected resist layer leaving a resist having a second thickness, wherein the second thickness is smaller than the first thickness.

    摘要翻译: 在一个实施方案中,本发明涉及一种处理抗蚀剂层的方法,包括以下步骤:提供具有第一厚度的抗蚀剂层,抗蚀剂层包含具有不稳定基团的聚合物; 使含有至少一种裂解化合物的涂层与抗蚀剂层接触,以在抗蚀剂层和涂层之间的界面处形成去保护的抗蚀剂层; 以及去除涂层和去保护的抗蚀剂层,留下具有第二厚度的抗蚀剂,其中第二厚度小于第一厚度。